图形电镀孔内无铜的产生原因分析

介绍了造成印制电路板图形电镀工艺过程中,孔内无铜产生的原因,根据流程分析给出了改善此缺陷的方向。     

版图图形特征对铜化学研磨的影响

Copper chemical mechanical polishing （CMP） is influenced by geometric characteristics such as line width and pattern density, as well as by the more obvious parameters such as slurry chemistry, pad type, polishing pressure and rotational speed. Variations in the copper thickness across each die and across the wafer can impact the circuit performance and reduce the yield. In this paper, we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors. Under the same process conditions, the pattern density, the line width and the line spacing have a strong influence on copper dishing, dielectric erosion and topography. The test results showed： the wider the copper line or the spacing, the higher the copper dishing; the higher the density, the higher the dielectric erosion; the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

版图图形特征对铜电镀工艺的影响

铜电镀工艺后表面的不平整度通常取决于版图关键特征,包括线宽,线间距和金属密度。本文设计了一款测试芯片并在一家半导体厂加工制造。版图特征效应被真正的测试数据所检查和验证。通过分析金属蝶形、介质腐蚀、金属厚度和SEM照片,得出一些结论。线宽是决定表面形貌及产生铜金属蝶形和介质层腐蚀的最关键因素。经过铜电镀工艺发现,铜线越细铜生长的越厚,铜线越宽铜金属蝶形越大,发现了3种典型表面形貌。而且,通过测试数据,量化版图特征的影响并用曲率增强加速剂覆盖率的理论解释,这可以用于开发铜电镀工艺模型和开展可制造性设计研究。     

图形电镀铜的常见缺陷及故障排除

本文主要阐述印制电路板生产中图形电镀铜常见缺陷及成因,查找影响其品质的因素和工序并结合相关生产制定相应的预防措施,有效提高产品质量。     

一种PCB电镀铜颗粒成因及机理分析

在PCB电镀生产过程中主要缺陷有以下几种,铜粒,凹痕﹑凹点﹑板面烧焦﹑层次电镀﹑表面氧化等;在这几种表面缺陷中铜粒的影响极为严重,且难以修理和返工。现对全板硫酸铜电镀后出现的一种有规律的板面铜颗粒的产生原因,及其反应机理分析,以便解决此类问题。     

一种采用不溶性阳极板的印制电路板酸性电镀铜技术

文章介绍了一种采用不溶性阳极板的酸铜电镀技术,相较于传统的可溶性阳极酸性电镀铜技术,具有显著的优势.该技术采用氧化–还原电子对"溶铜"技术"溶解"纯铜粒以补充镀液中消耗的铜离子,铜源成品价格较低;避免传统磷铜阳极中释放出来的磷污染槽液,影响电镀效果;避免含磷废液的产生和排放,降低环保负担和健康风险;避免阳极析氧,降低有...     

线路板图形电镀铜针孔（凹坑）的形成机制及防治对策研究

图形电镀针孔是采用传统压缩空气搅拌的酸性电镀铜工艺长期、普遍存在的一个问题。在电镀铜过程中，铜缸溶液中的气泡在上升的过程中容易附于干膜边缘，由于该气泡的滞留，使得该区域镀不上铜，形成凹坑；表现为在线条、焊盘、SMT上形成大小0．03—0．12毫米的光亮锥形孔；针孔的出现对于目前线宽发展为0．075毫米甚至0.05毫米的线条是实现不了图形电镀加工工艺的，而对于有特性阻抗控制要求的线路板，针孔的出现使得线条不能达到要求的阻抗值；     

一种40 nm MOSFET版图相关的波动模型建立

针对版图邻近与工艺波动因素对40 nm MOSFET器件物理效应变化和性能波动的影响进行分析,提出一种基于BSIM4.5的新型模型,修正原有模型的阈值电压和迁移率机制,有效地实现了版图邻近效应的建模。该模型主要考虑了相邻栅极间距psf和pss,相邻有源区的横向间距sodx1和sodx2,以及纵向间距sody对器件性能的影响。基于国内先进的40 nm工艺平台,对器件的Vthsat,Idsat,Vthlin和Idlin性能进行监测,得到相邻栅极间距对饱和电流和阈值电压分别有15%和30 mV的影响,横纵向有源区间距对饱和电流和阈值电压分别有1.5%和4 mV的影响,从而得到拟合度较好的仿真模型。结果表明,建立的模型能够有效降低结构仿真误差,大大提高设计人员的设计效率和准确性。     

铜电镀和钻化学镀沉积的监测

最新的研究将CVS监测技术扩展到分析有机破坏性产品中。本文讨论了用一种光谱分析技术代替电位滴定法可以不使用试剂就能对铜进行分析的方法。化学镀沉积槽的在线控制也在本文中被提到。     

一种新型铜槽模型对电镀均匀性提升的研究

文章主要根据传统的电镀铜理论,建立了一个新型的镀铜槽模型,对阴极电流传输方式、阴极冷冻方式、夹具优化、阳极挡板调整、阴阳极之间的距离等方面进行优化,电流从整流机传输至飞巴顶部再均分至夹具的传输方式,电流分布尖端效应影响明显处进行挡板、打孔处理,优化了电力线的分布,达到了提高垂直电镀线电镀厚度均匀性目的;实验结果表明:整个飞巴的极差小于8.5mm,COV达到4.8%,效果显著。     

An electroplating topography model based on layout-dependent variation of copper deposition rate

A layout-pattern-dependent electroplating model is developed based on the physical mechanism of the electroplating process.Our proposed electroplating model has an advantage over former ones due to a consideration of the variation of copper deposition rate with different layout parameters during the process.The simulation results compared with silicon data demonstrate the improvement in accuracy.     

Effects of pattern characteristics on the copper electroplating process

The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width,line spacing and metal density.A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process.By checking test data such as field height,array height,step height and SEM photos,some conclusions are made.Line width is a critical factor of topographical shapes such as the step height and height difference.After the electroplating process,the fine line has a thicker copper thickness,while the wide line has the greatest step height.Three typical topographies, conformal-fill,supper-fill and over-fill,are observed.Moreover,quantified effects are found using the test data and explained by theory,which can be used to develop electroplating process modeling and design for manufacturability (DFM) research.     

通孔电镀铜填孔浅析

电子产品朝更轻、更薄、更快方向发展的趋势,使印制电路板在高密度互连技术上面面临挑战。微堆叠孔技术是一种用来产生高密度互连的方法。通孔的填充介质目前主要有三种,分别为导电膏、树脂、纯铜。比较此三种填充方式,纯铜填孔技术工艺流程短,可靠性高。该文介绍了通孔填孔的反应机理,并论述了通孔填孔电镀技术的优势。     

基于微电铸的非硅MEMS加速度传感器

简单介绍了Silicon Design公司开发的非硅MEMS传感器的设计、工艺、输出信号的处理技术.通过巧妙设计和使用铸Ni技术成功地改善了梁的扭摆特性.实测结果表明,10 g产品的输出交流噪声有效值和漂移被分别控制在0.4 mV和4 mV;50 g产品虽然漂移偏大,但其线性系数K2还是达到了10-3～10-4的水准.     

Fabrication of high aspect ratio copper nanowires using supercritical CO2 fluids electroplating technique in AAO template

This study utilizes the supercritical and post-supercritical electroplating technique, to fabricate copper nano-wires inside ultra-high aspect ratio Anodic Aluminum Oxide templates (AAO templates). Comparisons of the electroplating capabilities and results were made between these methods and the more common traditional electroplating techniques. Under identical experimental conditions and on ultra-high aspect ratio AAO template with thickness of 60 µm (aspect ratio of 1:490), it is evident from the results that the supercritical electroplating process has the fastest electroplating velocity of the three processes (~1.33 µm/min), followed by post-supercritical electroplating (~1 µm/min) and traditional electroplating is the slowest (~0.67 µm/min). This study also discusses the electroplating quality of the copper nano-wires. Samples were sliced along the cross-section, and Field Emission Scanning Electron Microscopy (FESEM) was utilized to observe the copper nano-wires. X-Ray Diffraction (XRD) was used to observe that the crystal structures is polycrystalline, and with the use of equations it is determined that grain size will not be severely affected by changes in current density and supercritical pressure in themselves, but instead the different processes do produce an evident change. The grain size achieved with supercritical electroplating is the smallest, followed by the post-supercritical electroplating, and the largest was given by the traditional electroplating process. Through these results it can be proved that supercritical electroplating process indeed provides grain refinement capabilities. The supercritical fluid-enabled electroplating process utilized for these experiments does not need addition of any surfactants to aid filling of the structures, but only relies on the intrinsic properties of supercritical fluids to achieve complete filling of nano-holes, and because there are no surfactants, we can achieve higher degree of purity in the copper nano-wires.     

The influence of ultrasonic agitation on copper electroplating of blind-vias for SOI three-dimensional integration

Three-dimensional (3D) integration, which employs through-silicon-vias (TSVs) to electrically interconnect multiple-stacked chips, is a promising technology for significant reduction in interconnect delay and for hetero-integration of different technologies. To fabricate void-free TSVs, this paper presents a copper electroplating technique with the assistance of ultrasonic agitation to fill blind-vias, and discusses the influence of ultrasonic agitation on copper electroplating. Blind-vias with an aspect ratio of 3:1 are used for copper electroplating with both direct current (DC) and pulse-reverse current modes, combined with either ultrasonic agitation or mechanical agitation. Experimental results show that blind-vias with small aspect ratio can be completely filled using pulse-reverse current, regardless of the agitation methods. For DC, ultrasonic agitation is superior to mechanical agitation for copper electroplating in filling void-free vias. These results indicate that agitation, though is a secondary control factor to pulse-reverse current, can enhance mass transfer in blind-vias during copper electroplating and can improve the filling capability of copper electroplating.     

Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias

Three-dimensional (3D) integration is emerging as an attractive technology to continue Moore’s law through the integration of multi-stacked chips interconnected with through-silicon-vias (TSVs). To address the challenge in filling high aspect-ratio TSVs with copper, this paper reports an improved bottom-up copper electroplating (BCE) technique by introducing a glass transfer wafer, which is temporarily bonded with the device wafer to provide a copper seed layer. As the copper seed layer on the transfer wafer covers the through-holes, copper is electroplated from the bottom seed layer to the top opening of the through-holes without forming any voids or seams. This avoids the time consuming sealing process in conventional BCE, which normally takes 3-5 h. Thanks to the mechanical support of the transfer wafer, the device wafer can be thinned to several tens of micrometers. Using this technique, TSVs with diameter of 5 μm and aspect-ratio of 13:1 have been achieved. Based on the improved BCE technique, a through-via type 3D integration strategy is developed.     

电镀废液回收铜粉的化学镀银工艺及其电磁屏蔽性能

采用高频超声脉冲电解法从电镀铜废液中回收制备枝晶状的铜粉,并在铜粉表面进行化学镀银以制备电磁屏蔽用银包铜粉,采用SEM、EDS、XRD、TEM等对其进行形貌和组分分析,研究了银包铜粉复合涂层的导电性能和电磁屏蔽性能。结果表明,经过表面化学镀银可以有效地避免铜粉的氧化;涂层的电磁屏蔽性能与银包铜粉的添加量紧密相关,当涂层中银包铜粉质量分数为60%时,其电磁屏蔽效率高达52 dB。