基于性能驱动的工艺映射算法

用多级逻辑实现控制器的逻辑综合,工艺映射是其中的一个重要步骤。本文叙述的工艺映射算法TTMAP,是在映射过程中考虑了电路的时延与芯片面积等性能因素,在多级逻辑综合中将因子化的逻辑函数映射为CMOS的串并赶电路单元,产生可布图的网表文件。本算法在比利时HMEC研究中心开发,为多级逻辑综合系统MLL中的一个模块。经实例运行,与美国加州大学柏克莱分校的MISⅡ软件相比,本算法的结果较优。     

高性能单片存贮器

本文包括三篇译文: (1)“高性能单片存贮器”——介绍IBM360/85系统等应用的高速双极缓冲存贮器的系统考虑、逻辑型式以及外围电路和使用情况。 (2)“64位平面双扩散存贮器芯片”——介绍上述存贮器所用的双极存贮芯片、工艺结构,布线图形和器件性能。 (3)“一种新型高性能双极单片存贮单元”——介绍上述存贮器阵列单元的电路原理、工艺图形设计及性能参数。     

多级逻辑面积优化设计方法

该方法应用于超大规模集成电路的设计过程。逻辑优化是这一过程中的重要步骤。经优化后产生主题图质量的好坏,直接影响到最后的设计结果。该文针对主题图面积的优化问题,提出了“多级逻辑面积优化”设计方法。该方法通过“逻辑等价变换”技术,达到进一步优化主题图面积的目的。     

逻辑函数的双逻辑综合与优化

针对传统布尔逻辑在电路面积优化中存在的不足,提出了一种用传统布尔逻辑和Reed-Muller(RM)逻辑相结合的双逻辑优化算法.通过将原逻辑函数的乘积项转化为不相交乘积项,并利用不相交乘积项的位操作,将逻辑函数的覆盖分成2个部分,使之分别适合布尔逻辑综合和RM逻辑综合;同时提出了适合双逻辑函数的逻辑功能验证方法.双逻辑优化算法用C语言编程实现并用MCNC标准电路进行测试.实验结果表明,与单一的布尔逻辑综合结果相比,在绝大多数情况下文中算法可使电路面积获得进一步优化.     

逻辑再优化设计方法

本方法应用于超大规模集成电路的设计过程,逻辑分解的优化是这一过程的重要步骤,优化后产生主题图质量的好坏,直接影响到最后的设计结果,本文针对主题图延时和面积的优化问题,提出了“逻辑再优化”设计方法,该方法通过“逻辑等变换”技术,达到进一步优化主题图面积和延时性能的目的。     

逻辑再优化设计方法

本方法应用于超大规模集成电路的设计过程。逻辑分解的优化是这一过程中的重要步骤。优化后产生主题图质量的好坏 ,直接影响到最后的设计结果。本文针对主题图延时和面积的优化问题 ,提出了”逻辑再优化”设计方法。该方法通过“逻辑等价变换”技术 ,达到进一步优化主题图面积和延时性能的目的     

组合逻辑电路中的竞争与冒险

组合逻辑电路是《数字逻辑电路》中的主要内容之一。一般教材在讨论这部分内容时为了突出重点,都是以理想情况为基点而展开的,也就是说忽略了电路中的布线及门电路的延迟,电路中信号的变化也认为是“立即”完成的。但实际中,信号通过导线及门电路都有一个传输延迟时间,信号的变化也有一定的过渡过程,因此,理想情况下设计的组合逻辑     

低功耗多电源多地电压多米诺电路

设计了一种低功耗的多电源多地电压多米诺电路。该电路在多电源电压技术的基础上,通过提高地电压并采用共阱工艺降低功耗及优化面积。该设计采用Charter 0.35μm 2P4M N阱CMOS标准工艺完成。Spectre仿真结果表明,在相同的速度下,多电源多地电压多米诺电路比传统的多米诺电路的功耗减少了25%左右。     

电路图的自动生成技术

本文提出一种从版图自动生成电路逻辑图的方法。此方法主要是从MOS IC版图中提取出电路的逻辑关系,而后根据这些逻辑关系由计算机自动生成电路的逻辑图,供版图的逻辑验证之用。此方法应用了排队技术和布局优化技术等,使生成的电路逻辑图符合一般的要求,节省了面积。它能支持自顶向下的设计过程,已用FORTRAN语言程序化,并已在不同的MOS IC电路绘图中得到应用。     

基于损耗均分模型的控制逻辑优化

实际的工业自动化控制过程中,存在着一种根据特定需求启动和关闭某些设备的运行方法.这种方法需要综合考虑使用设备的多种条件,如果按照传统的排列组合等方式编程,程序将会十分繁复、容易出错.本文通过数学上的分析,给出了一套更优化的逻辑,使得程序更加简明易查.     

Power Droop Testing

High-performance digital ICs manufactured in deep-submicron technologies tend to draw considerable amounts of power during operation. Power droop describes the impact of power consumption transients on the logic values of a circuit's signal lines and, ultimately, on the correctness of the circuit's operation. Although power droop could cause an IC to fail, such failures cannot be screened during testing, because conventional fault models do not cover them. In this article, we present a technique for screening such failures. We propose a heuristic method to generate test sequences that create worst-case power drop by accumulating high- and low-frequency effects. We employ a dynamically constrained version of the classical D-algorithm, which generates new constraints on the fly, for test generation. The obtained patterns can be used for manufacturing test and early silicon validation. We have implemented a prototype ATPG to demonstrate the feasibility of this approach.     

基于多目标演化算法的逻辑电路设计

电路演化设计是新兴的研究热点,通过对电路演化设计的基本原理的介绍,提出了基于演化算法特别是改进的遗传算法(GeneticAlgorithm),根据具有一定逻辑功能的真值表,依据多个设计目标,以较少的运算量和较高的效率来演化设计出一个较优的逻辑电路。通过对几个具体实例的研究分析,说明了该设计思想的有效性和先进性。     

基于演化算法的全加器优化设计

演化硬件研究工作中的一个重要研究内容就是电路优化设计,电路优化设计有望实现复杂电路的自动设计并获得新颖、优化的设计结果,因而成为国际性的研究热点。将演化算法引入全加器电路的优化设计中,引入了新的个体评估机制并提出了适用于全加器演化的演化算法。通过仿真实验验证了算法的有效性。     

用于高速逻辑电路优化的改进Retiming算法

时序重排是一种同步时序电路性能优化的重要方法,文中提出了一种改进时序重排算法,使时序重排可以更有效地与其经组合优化算法结合起来,共同提高同步时序电路的速度,在各种不同的测试电路上得到的实验结果显示,这种算法在与其它组合优化方法的结合上,较以往的时序重排算法有很大的改进。     

Optimization of digital holographic setup by a fuzzy logic prediction system

In this study, the optimization of the digital holography setup is achieved by a using fuzzy logic prediction system. In fact, when this optimization process is experimentally performed, some parameters are changed in the setup. These parameters affect directly the obtained image quality after a reconstruction process, which is determined by normalized root mean square. The aim of this study is to achieve the optimization of digital holographic setup by using both experimental and fuzzy logic prediction systems. Furthermore, the required time during the experimental optimization can be lowered by using a numerical method like the fuzzy logic prediction system. Here, the experimental optimization results and the optimization results obtained by the fuzzy logic prediction system are compared. It is offered that the designed experimental system can be optimized by using an artificial intelligent tool. The applied fuzzy logic prediction model is used the first time for optimization of hologram recording setup. As a result, it is reached a conclusion that the optimization of digital holographic setup can be numerically performed by the fuzzy logic prediction system. Moreover, while digital holographic setup is experimentally designed, the required time for optimization is reduced, as well.     

基于整数编码的分布式估计单元重组算法

分布式估计算法(estimation of distribution algorithms,EDAs)源于遗传算法,是一种对群体采用宏观方法建模和模拟的新型优化算法.本文根据动态重组制造单元的一般原则,针对制造单元重组问题,提出了基于整数编码的分布式估计制造单元重组算法,通过概率图模型取代传统的交叉、变异等遗传算法操作,并创新的采用轮盘赌方法将EDAs的编码由二进制数改进为整数,降低了编码的长度,开拓了其应用范围.该算法根据两个定量指标,将动态逻辑单元重组问题转化成一个简单的多目标组合优化问题模型,并能真实反映单元重组的本质要求.最后给出实例验证.     

Generating Java Compiler Optimizers Using Bidirectional CTL

There have been several research works that analyze and optimize programs using temporal logic. However, no evaluation of optimization time or execution time of these implementations has been done for any real programming language. In this paper, we present a system that generates a Java optimizer from specifications in temporal logic. The specification is simpler, and the generated optimizers run more efficiently than previously reported work. We implemented a new model checker for a bidirectional CTL (computational tree logic) called CTL_bd, which is equivalent to CTL-FV [Lacey, D., Jones, N.D., Van Wyk, E. and Frederiksen, C.C.: Compiler optimization correctness by temporal logic. Higher-Order and Symbolic Computation, Vol. 17, No. 3, pp. 173–206, 2004] after removing free variables. The model checker can check future and past temporal CTL operators symmetrically without any conversion. We also present a new specification language based on the bidirectional CTL that can express typical optimization rules very naturally. By adding rewriting conditions to allow for temporary variables and considering real-world language features such as exceptions, the system can perform optimization of Java programs. So far, a compiler optimizer using temporal logic was assumed to be impractical, because it consumes too much time. However, with our method, the generated Java compiler optimizer can compile seven of the SPECjvm98 benchmarks with a compile time from 4 seconds to 4 minutes.     

Toward hardware-redundant, fault-tolerant logic for nanoelectronics

This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit's logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit's reliability tends to reach a stationary state as its logical depth increases.