Optimization of Microscale Thermoelectric Cooling (TEC) Element Dimensions for Hotspot Cooling Applications

Microscale thermoelectric cooling elements (TECs) are being proposed to cool down an integrated circuit to maintain its performance. The maximum cooling power of microscale TECs is significantly reduced by the interfacial resistance. For our particular application, we calculate the optimal dimension of the TECs, made of Bi₂Te₃, that reduce the temperature at a hotspot on an IC chip by 10°C. By the one-dimensional analytical model that we developed and numerical solutions of TEC equations using MATLAB^©, we obtain performance characteristics that relate the cooling power density to other control variables and material constants. The optimal dimension of microscale TECs is calculated for cooling at a hotspot region by a range of temperature differences, for example from 10°C to 50°C. Further, the percentage change in the optimal thickness for various thermal resistances and electrical contact resistances can be predicted. These results act as a good guideline for two-dimensional analysis and assembly of TECs.     

Mini-Contact Enhanced Thermoelectric Cooling of Hot Spots in High Power Devices

Cooling hot-spots with high heat flux (e.g., >1000 W/cm²) is becoming one of the most important technical challenge in today's integrated circuit industry. More aggressive thermal solutions, than would be required for uniform heating, are highly desired. Recently, solid state thermoelectric coolers (TECs) have received more attention for hot-spot thermal management. However, present day TECs typically have cooling flux much lower than heat flux in the hot-spots. In this work, we reported an innovative technique-TE Mini-contact-to significantly increase cooling flux of TECs for the application in hot-spot cooling. A chip package featuring a TE Mini-contact cooler integrated with conventional integrated heat spreader and heat sink is designed. The cooling performance of such chip package has been investigated by using a 3-D numeric model. It is found that the cooling in the hot-spot (1250 W/cm², 400 mum by 400 mum) can be about 19 degC better in the proposed package than that achieved in the conventional chip package without TEC. The effects of trench, die thickness, and TEC misalignment on the cooling of the hot-spot are also discussed.     

Enhancing Performance of Thermoelectric Coolers Through the Application of Distributed Control

The primary drawback of thermoelectric coolers (TECs) for electronics cooling applications is their thermodynamic inefficiency due to material limitations. The present work considers a control strategy to improve the overall coefficient of performance in an engineering system instead of addressing material shortcomings. Typical TECs are composed of several individual thermocouples that are powered in series and remove heat in parallel. If one of the numerous thermocouples is powered, all the thermocouples receive the some power whether or not they are needed. The fact that chips heat nonuniformly provides an opportunity for performance enhancement, by sensing and controlling the power to individual couples within the device. The current work presents evidence that applying distributed control to TEC operation can realize appreciable improvement in performance. Compared to monolithic cooling devices, a distributed control strategy can realize a factor of 2 increase in performance for the device studied. Additionally, this type of control can be used in conjunction with many of the existing material-based research initiatives to further compound the benefits.     

Current and future miniature refrigeration cooling technologies for high power microelectronics

Utilizing refrigeration may provide the only means by which future high-performance electronic chips can be maintained below predicted maximum temperature limits. Widespread application of refrigeration in electronic packaging will remain limited, until the refrigerators can be made sufficiently small so that they can be easily incorporated within the packaging. A review of existing microscale and mesoscale refrigeration systems revealed that only thermoelectric coolers (TECs) are now commercially available in small sizes. However, existing TECs are limited by their maximum cooling power and low efficiencies. A simple model was constructed to analyze the performance of both existing and predicted future TECs, in an electronic packaging environment. Comparison with the cooling provided by an existing high-performance fan shows that they are most effective for heat loads less than approximately 100 W, but that for higher heat loads, fan air cooling actually yields a lower junction temperature. Thermal resistance between the refrigerator and the chip is not as critical as the thermal resistance between the refrigerator and the ambient air.     

Finite element analysis of miniature thermoelectric coolers with high cooling performance and short response time

The miniature thermoelectric cooler (TEC) is a promising device for microelectronics applications with high cooling performance and short response time. In this paper, a comprehensive numerical analysis focusing on the cooling performance and response time of the TEC is performed by finite element methods (FEMs). The effects of load current, geometric size, ratio of length to cross-sectional area and substrate's thermal resistance on the performance of the TEC are studied. The results show that the performance of TECs has been improved by reducing the TEC's size and ratio of length to cross-sectional area, resulting in a maximum cooling temperature difference of 88 °C, a cooling power density of 1000 W cm⁻² and a short response time on the order of milliseconds. Furthermore, the substrate, which hinders the circulation of heat between the TEC and the atmosphere, also has a significant influence on the performance of the TEC.     

Analysis and Control of Equivalent Physical Simulator for Nanosatellite Space Radiator

A realistic prediction of the in-orbit transient performance of a nanosatellite space radiator requires a ground-based equivalent space radiator with a small size, simple configuration, and fast response. For this purpose, we present in this paper the design concept, operating principle, and analysis algorithm of a novel equivalent physical simulator (EPS) consisting of a thermoelectric cooler (TEC), a plate-fin heat sink, and a forced cooling fan. The TEC-based EPS achieves the purpose of simulating the in-orbit transient heat radiation in earth's atmospheric environment by adapting two key parameters: the TEC cooling capacity and the thermal resistance of the heat sink cooling fan. This paper offers results of in-depth numerical parametric studies leading to an EPS design that enables robust simulations under both hot-case and cold-case operations. In addition, we present the design and evaluation of a fuzzy controller for the EPS as an attractive alternative to the traditional PID controller. The fuzzy control presented here will have other potential thermal control applications where TECs and forced cooling heat sinks are employed.      

Nanoscale Thermal Transport and Microrefrigerators on a Chip

In this paper we review recent advances in nanoscale thermal and thermoelectric transport with an emphasis on the impact on integrated circuit (IC) thermal management. We will first review thermal conductivity of low-dimensional solids. Experimental results have shown that phonon surface and interface scattering can lower thermal conductivity of silicon thin films and nanowires in the sub-100-nm range by a factor of two to five. Carbon nanotubes are promising candidates as thermal vias and thermal interface materials due to their inherently high thermal conductivities of thousands of W/mK and high mechanical strength. We then concentrate on the fundamental interaction between heat and electricity, i.e., thermoelectric effects, and how nanostructures are used to modify this interaction. We will review recent experimental and theoretical results on superlattice and quantum dot thermoelectrics as well as solid-state thermionic thin-film devices with embedded metallic nanoparticles. Heat and current spreading in the three-dimensional electrode configuration, allow removal of high-power hot spots in IC chips. Several III-V and silicon heterostructure integrated thermionic (HIT) microcoolers have been fabricated and characterized. They have achieved cooling up to 7 /spl deg/C at 100 /spl deg/C ambient temperature with devices on the order of 50 /spl mu/m in diameter. The cooling power density was also characterized using integrated thin-film heaters; values ranging from 100 to 680 W/cm/sup 2/ were measured. Response time on the order of 20-40 ms has been demonstrated. Calculations show that with an improvement in material properties, hot spots tens of micrometers in diameter with heat fluxes in excess of 1000 W/cm/sup 2/ could be cooled down by 20 /spl deg/C-30 /spl deg/C. Finally we will review some of the more exotic techniques such as thermotunneling and analyze their potential application to chip cooling.     

Thermal stability analysis of AlGaAs/GaAs heterojunction bipolartransistors with multiple emitter fingers

A numerical electro-thermal model was developed for AlGaAs/GaAs heterojunction bipolar transistors (HBT's) to describe the base current, current gain and output power dependence on junction temperature. The model is applied to microwave HBT devices with multi-emitter fingers. The calculated results of the common-emitter, current-voltage characteristics in the linear active region show a “current crush” effect due to inherent nonuniform junction temperature, current density and current gain distribution in the device. The formation of highly localized high temperature regions, i.e., hot spots, occur when the device is operating beyond the current-crush point. This thermally induced current instability imposes an upper limit on the power capability of HBT's. The dependence of this effect on various factors is discussed. These factors include the intrinsic parameters such as the base current ideality factor, the “apparent” valence band discontinuity, and the temperature coefficient of the emitter-base turn-on voltage, as well as the extrinsic factors such as the emitter contact specific resistance, the substrate thermal conductivity and the heat source layout     

Effect of Local Hot Spots on the Maximum Dissipation Rates During Flow Boiling in a Microchannel

One of the most promising technologies to replace air-cooling of micro-processor chips is flow boiling in microchannels. The very high heat flux dissipation from micro-processor chips is highly non-uniform due to the presence of multiple localized hot spots usually related to the localization of bridges and gate oxide shorts. Previous studies focused on the performance of microchannels under uniform heating conditions. Recently, Revellin and Thome (see Int. J. Heat Mass Transf., vol 51, no.5-6, p. 1216-25, 2008) have proposed a new theoretical model to predict the critical heat flux (CHF) in microchannels. This model has been modified here to take into account a non-uniform axial heat flux along a microchannel. The model is used here to perform a local hot spot study to investigate the effects of fluid, saturation temperature, mass flux, microchannel diameter, heated length, size, location and number of hot spots as well as the distance between two consecutive hot spots. Based on the present simulations, to best dissipate a hot spot's heat flux, microchannel heat sinks should follow the following recommendations for a channel of fixed length: determine the optimum channel diameter for the fluid (typically either very small or large is best), utilize as high of mass flux as feasible, and design with as low of saturation temperature as possible. Furthermore, the local hot spot size should be as small as possible, the number of local hot spots as few as possible and the distance between two hot spots as large as possible. Utilizing the present numerical method for individual microchannels arranged in parallel in a multi-microchannel cooling element, it is possible to simulate the entire power dissipation profile of a microprocessor die for local limits of CHF.     

Comprehensive System-Level Optimization of Thermoelectric Devices for Electronic Cooling Applications

Advanced cooling solutions are needed to address the growing challenges posed by future generations of microprocessors. This paper outlines an optimization methodology for electronic system based thermoelectric (TE) cooling. This study stresses that an optimum TE cooling system should keep the electronic device below a critical junction temperature while utilizing the smallest possible heat sink. The methodology considers the electric current and TE geometry that will minimize the junction temperature. A comparison is made between the junction temperature minimization scheme and the more conventional coefficient of performance (COP) maximization scheme. It is found that it is possible to design a TE solution that will both maximize the COP and minimize the junction temperature. Experimental measurements that validate the modeling are also presented.     

光纤耦合激光器驱动与控制技术研究

针对一种将多个半导体激光器(LD)芯片串联驱动,通过光纤耦合进行功率合成,构成光纤耦合高功率输出激光模块的特殊驱动要求,研发了小型化高效率激光电流源组件和小型化高效率半导体制冷(TEC)LD模块温度控制组件。组件工作温度范围为-45℃～55℃,实验证明达到了设计性能指标要求。建立了LD模块驱动电流源电路的数学模型,提出了LD模块电流源控制电路的数字化实现方法,并利用ADuC831单片机实现了数字化设计。给出了一种基于TEC的LD模块温度控制组件的结构,建立了简化、实用的温度控制系统数学模型,对TEC的性能系数ξ、控制端的热量Qc和TEC的工作电流I进行了寻优控制,减小了激光器输出波长随温度的漂移。     

Experimental and numerical study of 3D stacked dies under forced air cooling and water immersion cooling

3D stacked die structure is a promising architecture to realize small feature size and enhance electronic performance. However, thermal performance in 3D stacked die has aroused extensive attention for its high density integration. In this paper, a stacked dummy die structure integrated with polyimide heater inside is presented to investigate the thermal behavior of 3D stacked dies. One-dimensional thermal resistance network is built and calculated to analyze thermal resistance distribution of the stacked dies. Under natural convection, the thermal resistance of convective heat transfer greatly influences total thermal resistance and limits heat dissipation ability of stacked dies. To significantly reduce the thermal resistance of convective heat transfer, forced air cooling and water immersion cooling have been applied in the stacked die structure. Experiment and numerical simulation have been conducted in this work. In the experiment, forced air cooling and water immersion cooling systems are set up to cool down the stacked die structure. The temperature dependence of the stacked die structure is obtained by thermocouples. The measured thermal resistances between junction and ambient environment of the stacked die structure decrease to 7.6 °C/W under forced air cooling and to 0.6 °C/W under water immersion cooling, respectively. Then heat dissipation abilities of forced convection cooling for the stacked die structure are analyzed. Simulation models are built for experimental validation and further thermal analysis. Temperature influences on the internal structure of the stacked dies with different power map are discussed. The simulation results can well capture the experimental results with 5.8% variation under forced air cooling and with 7.4% variation under water immersion cooling when total power of 3 W is applied.     

On-chip solid-state cooling for integrated circuits using thin-film microrefrigerators

An overview of recent advances in solid-state cooling utilizing thin-film silicon germanium-based microrefrigerators is given. Key parameters affecting micro cooler performance are described. A 3-/spl mu/m thick 200/spl times/ (3 nm Si/12 nm Si/sub 0.75/Ge/sub 0.25/) superlattice device can achieve maximum cooling of 4/spl deg/C at room temperature, maximum cooling power density of 600 W/cm/sup 2/ for 40-/spl mu/m diameter device and fast transient response on the order of tens of micro-seconds independent of the device size. Three-dimensional electrothermal simulations show that individual microrefrigerators could be used to remove hot spots in silicon chips with minimal increase in the overall power dissipation.     

Thermal solutions for discrete and wafer-level RF MEMS switch packages

In discrete radio frequency (RF) microelectromechanical systems (MEMS) packages, MEMS devices were fabricated on silicon or gallium arsenide (GaAs) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 /spl Omega/ exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis has been performed to study the heat dissipation at the switch contact area. The goal is to control the "hot spots" and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials has been considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and low-temperature cofired ceramic (LTCC) have been studied. Thermal experiments have been conducted to measure the temperature at the contact area and its vicinity as a function of dc and RF powers. Several solutions in material selection and package configurations have been explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity. For discrete MEMS packages, placing the die inside a copper cavity on the substrate provides significant heat dissipation. For wafer-level packages, thin diamond coatings on the substrate could reduce the hot-spot temperature considerably.     

Electric Power Generation from Thermoelectric Cells Using a Solar Dish Concentrator

In this paper, design details, theoretical analysis, and outcomes of a preliminary experimental investigation on a concentrator thermoelectric generator (CTEG) utilizing solar thermal energy are presented. The designed CTEG system consisted of a parabolic dish collector with an aperture diameter of 1.8 m used to concentrate sunlight onto a copper receiver plate with 260 mm diameter. Four BiTe-based thermoelectric cells (TEC) installed on the receiver plate were used to convert the concentrated solar thermal energy directly into electric energy. A microchannel heat sink was used to remove waste heat from the TEC cold side, and a two-axis tracking system was used to track the sun continuously. Experimental tests were conducted on individual cells and on the overall CTEG system under different heating rates. Under maximum heat flux, a single TEC generator was able to produce 4.9 W for a temperature difference of 109°C, corresponding to 2.9% electrical efficiency. The overall CTEG system was able to produce electric power of up to 5.9 W for a 35°C temperature difference with a hot-side temperature of 68°C. The results of the investigation help to estimate the potential of the CTEG system and show concentrated thermoelectric generation to be one of the potential options for production of electric power from renewable energy sources.     

Study on a cooling system based on thermoelectric cooler for thermal management of high-power LEDs

To improve the heat dissipation of high-power light-emitting diodes (LEDs), a cooling system with thermoelectric cooler (TEC) is investigated. In the experiment, the 6 × 3 W LEDs in two rows are used to compose the light source module and the environment temperature is 17 °C. The temperatures of heat dissipation substrate of LEDs and cooling fins of a radiator are measured by K type thermocouples to evaluate the cooling performance. Results show that the temperature of the substrate of LEDs reaches 26 °C without TEC. However, it is only 9 °C when the best refrigeration condition appears. The temperature of the substrate of LEDs decreases by 17 °C since the heat produced by LEDs is absorbed rapidly by TEC and dissipated through the radiator, and the junction temperature of LEDs reaches only 45 °C which is much lower than the absolute maximum temperature of LEDs (120 °C). The experiment demonstrates that the cooling system with TEC has good performance.     

Self-Assembly for Integration of Microscale Thermoelectric Coolers

Optimum thermoelectric cooling (TEC) solutions often require the integration of component sizes inaccessible by common manufacturing techniques such as thin-film processing and robotic assembly. This work considers an application case in which small elements (100 μm to 300 μm thick) are optimal. A capillary self-assembly process is presented as a potential route to manufacturing TECs in these size ranges. A millimeter-scale demonstration of the assembly concept is presented and Monte Carlo simulation is used to study the scaling of the self-assembly approach to assemblies with more components. While assembly rate and system yield can be a challenge, several approaches are presented for increasing both rate and yield.     

On-chip high speed localized cooling using superlattice microrefrigerators

In this paper, we addressed heating problems in integrated circuits (ICs) and proposed a thin-film thermionic cooling solution using Si/SiGe superlattice microrefrigerators. We compared our technology with the current most common solution, thermoelectric coolers, by strengthening the advantages of its compatible fabrication process as ICs for easy integration, small footprint in the order of /spl sim/ 100/spl times/100 /spl mu/m/sup 2/, high cooling power density, 600W/cm/sup 2/ and fast transient response less than 40 /spl mu/s. The thermoreflectance imaging also demonstrated its localized cooling. All these features combined together to make these microrefrigerators a very promising application for on-chip temperature control, removing hot spots inside IC.     

芯片冷却中热电制冷器性能的实验研究

设计了电子芯片冷却实验装置,对热电制冷器在电子芯片冷却中的冷却效果和制冷性能进行了研究。实验结果表明,不仅热电制冷片热端冷却水流量是影响冷却效果的重要因素,而且热电电流和芯片功率与热电冷却性能也有着密切的关系。实验结果对热电冷却器的最佳冷却性能的确定具有一定的参考意义。     

Thermal Investigation of GaN-Based Laser Diode Package

We investigated thermal behavior of GaN-based laser diode (LD) packages as a function of cooling systems, die attaching materials, chip loading conditions, and optical performances. The electrical thermal transient technique was employed for the thermal measurement of junction temperature and thermal resistance of LD packages. The results demonstrate that the total thermal resistance of LD packages is controlled mainly by the packaging design rather than the chip structure itself. Significant changes in thermal resistance with input current were observed under a natural cooling system because of the sensitive change in the heat transfer coefficient with the change in temperature. Employment of PbSn as a die attachment was more advantageous over the Ag-paste in the thermal behavior of LD packages. The LD package with epi-down structure resulted in the lower thermal resistance compared to one with epi-up structure. A continuous increase in junction temperature was measured after lasing. It was attributed to an increase in the thermal resistance of LD when it took the optical power into an account. Effective input power was decreased by the lasing and led to high thermal resistance values.