Blind Stochastic Feature Transformation for Channel Robust Speaker Verification

To improve the reliability of telephone-based speaker verification systems, channel compensation is indispensable. However, it is also important to ensure that the channel compensation algorithms in these systems surpress channel variations and enhance interspeaker distinction. This paper addresses this problem by a blind feature-based transformation approach in which the transformation parameters are determined online without any a priori knowledge of channel characteristics. Specifically, a composite statistical model formed by the fusion of a speaker model and a background model is used to represent the characteristics of enrollment speech. Based on the difference between the claimant's speech and the composite model, a stochastic matching type of approach is proposed to transform the claimant's speech to a region close to the enrollment speech. Therefore, the algorithm can estimate the transformation online without the necessity of detecting the handset types. Experimental results based on the 2001 NIST evaluation set show that the proposed transformation approach achieves significant improvement in both equal error rate and minimum detection cost as compared to cepstral mean subtraction and Znorm. Kwok-Kwong Yiu received a BEng (Hons) degree in 1992 and an MPhil degree in 2000 from the Department of Electronic and Information Engineering, The Hong Kong Polytechnic University. He was a Research Associate at the same institute from 2000 to 2001. He is currently a PhD student and his supervisor is Dr. M.W. Mak. His research interests include speaker verification, neural networks, and channel compensation. Man-Wai Makreceived a BEng (Hons) degree in Electronic Engineering from Newcastle Upon Tyne Polytechnic in 1989 and a PhD degree in Electronic Engineering from the University of Northumbria at Newcastle in 1993. He was a Research Assistant at the University of Northmubria at Newcastle, from 1990 to 1993. He joined the Department of Electronic Engineering at the Hong Kong Polytechnic University as a Lecturer in 1993 and as an Assistant Professor in 1995. Since 1995, Dr. Mak has been an executive committee member of the IEEE Hong Kong Section Computer Chapter. He is currently the chairman of the IEEE Hong Kong Section Computer Chapter. Dr. Mak's research interests include speaker recognition and neural networks. Ming-Cheung Cheung received a BSc (Hons) degree in Information Technology from The Hong Kong Polytechnic University in 2002. Since November 2002, he has been an MPhil student at the Department of Electronic and Information Engineering of The Hong Kong Polytechnic University. His research interests include pattern recognition, neural networks, and fusion techniques for multimodal biometric authentication. Sun-Yuan Kung received his Ph.D. Degree in Electrical Engineering from Stanford University. In 1974, he was an Associate Engineer of Amdahl Corporation, Sunnyvale, CA. From 1977 to 1987, he was a Professor of Electrical Engineering-Systems, the University of Southern California. Since 1987, he has been a Professor of Electrical Engineering, Princeton University. Since 1990, he has served as an Editor-In-Chief of Journal of VLSI Signal Processing Systems. He served as a founding member and General Chairman of various international conferences, including IEEE Workshops on VLSI Signal Processing in 1982 and 1986 (L.A.), International Conference on Application Specific Array Processors in 1990 (Princeton) and 1991 (Barcelona), and IEEE Workshops on Neural Networks and Signal Processing in 1991 (Princeton), 1992 (Copenhagen) and 1998 (Cambridge, UK), the First IEEE Workshops on Multimedia Signal Processing in 1997 (Princeton), and International Computer Symposium in 1998 (Tainan).Dr. Kung is a Fellow of IEEE. He was the recipient of 1992 IEEE Signal Processing Society's Technical Achievement Award for his contributions on “parallel processing and neural network algorithms for signal processing”. He was appointed as an IEEE-SP Distinguished Lecturer in 1994. He received 1996 IEEE Signal Processing Society's Best Paper Award. He was a recipient of the IEEE Third Millennium Medal in 2000. He has authored more than 300 technical publications, including three books “VLSI Array Processors”, (Prentice Hall, 1988) (with Russian and Chinese translations), “Digital Neural Networks”, Prentice Hall, 1993, and “Principal Component Neural Networks”, John Wiley, 1996.     

Complex Infomax: Convergence and Approximation of Infomax with Complex Nonlinearities

Independent component analysis (ICA) for separating complex-valued sources is needed for convolutive source-separation in the frequency domain, or for performing source separation on complex-valued data, such as functional magnetic resonance imaging or radar data. Previous complex Infomax approaches that use nonlinear functions in the updates have proposed using bounded (and hence non-analytic) nonlinearities. In this paper, we propose using an analytic (and hence unbounded) complex nonlinearity for Infomax for processing complex-valued sources. We show by simulation examples that using an analytic nonlinearity for processing complex data has a number of advantages. First, when compared to split-complex approaches (i.e., approaches that split the real and imaginary data into separate channels), the shape of the performance surface is improved resulting in better convergence characteristics. We also show that using an analytic complex-valued function for the nonlinearity is more effective in generating the higher order statistics required to establish independence when compared to complex nonlinear functions, i.e., functions that are ℂ → ℂ This work was supported in part by the National Science Foundation Career Award, NSF NCR-9703161 (to TA) and the National Institutes of Health 1 R01 EB 000840-01 (to VC). Vince Calhoun received a bachelor’s degree in Electrical Engineering from the University of Kansas, Lawrence, Kansas, in 1991, master’s degrees in Biomedical Engineering and Information Systems from Johns Hopkins University, Baltimore, in 1993 and 1996, respectively, and the Ph.D. degree in electrical engineering from the University of Maryland Baltimore County, Baltimore, in 2002. He worked as a Senior Research Engineer in Psychiatric Neuro-Imaging at Johns Hopkins from 1993 until 2002. He is currently the Director of the Medical Image Analysis Laboratory and an associate adjunct professor at Yale University. He is associate editor of the IEEE signal processing letters and on the editorial board for the Journal of Human Brain Mapping. Dr. Calhoun is a member of the IEEE, the American Scientific Affiliation, the Organization for Human Brain Mapping, and the International Society for Magnetic Resonance in Medicine. He has organized workshops for human brain mapping (HBM), the society of biological psychiatry (SOBP), and the international conference of independent component analysis and blind source separation (ICA). He is currently serving on the IEEE Machine Learning for Signal Processing (MLSP) Technical Committee and was the general chair for MLSP 2005 in Mystic, CT. He works primarily with magnetic resonance imaging (functional imaging, diffusion tensor imaging, and structural imaging) and electroencephalography (EEG) data and is the author of more than 70 refereed articles in journals and conference proceedings in the areas of image processing, data fusion, adaptive signal processing, neural networks, statistical signal processing, and pattern recognition. Tülay Adalı received the B.S. degree from Middle East Technical University, Ankara, Turkey, in 1987 and the M.S. and Ph.D. degrees from North Carolina State University, Raleigh, in 1988 and 1992 respectively, all in electrical engineering. In 1992, she joined the Department of Electrical Engineering at the University of Maryland Baltimore County, Baltimore, where she currently is a professor. She has worked in the organization of a number of international conference and workshops including the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) and the IEEE International Workshop on Machine Learning for Signal Processing (MLSP). She was the general co-chair for the NNSP workshops 2001-2003. She is the past chair and a current member of the IEEE Machine Learning for Signal Processing Technical Committee and is serving on the IEEE Signal Processing Society conference board. She is an associate editor for the IEEE Transactions on Signal Processing and the Journal of VLSI Signal Processing Systems. She has also guest-edited a number of special issues for the IEEE Transactions on Neural Networks and the VLSI Signal Processing Systems on biomedical, multimedia, and data mining applications of neural networks. She has authored or co-authored more than 175 refereed publications in the areas of statistical signal processing, neural computation, adaptive signal processing, biomedical data analysis, bioinformatics, and communications. Dr. Adalı is the recipient of a 1997 National Science Foundation CAREER Award.     

Audio Fingerprinting: Nearest Neighbor Search in High Dimensional Binary Spaces

Audio fingerprinting is an emerging research field in which a song must be recognized by matching an extracted “fingerprint” to a database of known fingerprints. Audio fingerprinting must solve the two key problems of representation and search. In this paper, we are given an 8192-bit binary representation of each five second interval of a song and therefore focus our attention on the problem of high-dimensional nearest neighbor search. High dimensional nearest neighbor search is known to suffer from the curse of dimensionality, i.e. as the dimension increases, the computational or memory costs increase exponentially. However, recently, there has been significant work on efficient, approximate, search algorithms. We build on this work and describe preliminary results of a probabilistic search algorithm. We describe the data structures and search algorithm used and then present experimental results for a database of 1,000 songs containing 12,217,111 fingerprints. Ingemar J. Cox is currently Professor and Chair of Telecommunications in the Departments of Electronic Engineering and Computer Science at University College London and Director of UCL's Adastral Park Postgraduate Campus. He is currently a holder of a Royal Society Wolfson Fellowship. He received his B.Sc. from University College London and Ph.D. from Oxford University. He was a member of the Technical Staff at AT&T Bell Labs at Murray Hill from 1984 until 1989 where his research interests were focused on mobile robots. In 1989 he joined NEC Research Institute in Princeton, NJ as a senior research scientist in the computer science division. At NEC, his research shifted to problems in computer vision and he was responsible for creating the computer vision group at NECI. He has worked on problems to do with stereo and motion correspondence and multimedia issues of image database retrieval and watermarking. In 1999, he was awarded the IEEE Signal Processing Society Best Paper Award (Image and Multidimensional Signal Processing Area) for a paper he co-authored on watermarking. From 1997–1999, he served as Chief Technical Officer of Signafy, Inc, a subsiduary of NEC responsible for the commercialization of watermarking. Between 1996 and 1999, he led the design of NEC's watermarking proposal for DVD video disks and later colloborated with IBM in developing the technology behind the joint “Galaxy” proposal supported by Hitachi, IBM, NEC, Pioneer and Sony. In 1999, he returned to NEC Research Institute as a Research Fellow. He is a senior member of the IEEE, a Fellow of the IEE and a Fellow of the Royal Society for Arts and Manufactures. He is co-editor in chief of the IEE Proc. on Information Security and an associate editor of the IEEE Trans. on Information Forensics and Security. He is co-author of a book entitled “Digital Watermarking” and the co-editor of two books, ‘Autonomous Robots Vehicles’ and ‘Partitioning Data Sets: With Applications to Psychology, Computer Vision and Target Tracking’. This work was performed while the author was at NEC Research Institute, Princeton. ? [2002] IEEE, Reprinted, with permission, from Miller, M.L.; Rodriguez, M.A.; Cox, I.J.; Multimedia Signal Processing, 2002 IEEE Workshop on, 2002 Page(s): 182–185.     

Network-Adaptive Video Communication Using Packet Path Diversity and Rate-Distortion Optimized Reference Picture Selection

In this paper, we present error-resilient Internet video transmission using path diversity and rate-distortion optimized reference picture selection. Under this scheme, the optimal packet dependency is determined adapting to network characteristics and video content, to achieve a better trade-off between coding efficiency and forming independent streams to increase error-resilience. The optimization is achieved within a rate-distortion framework, so that the expected end-to-end distortion is minimized under the given rate constraint. The expected distortion is calculated based on an accurate binary tree modeling with the effects of channel loss and error concealment taken into account. With the aid of active probing, packets are sent across multiple available paths according to a transmission policy which takes advantage of path diversity and seeks to minimize the loss rate. Experiments demonstrate that the proposed scheme provides significant diversity gain, as well as gains over video redundancy coding and the NACK mode of conventional reference picture selection. Yi Liang received the Ph.D. degree in Electrical Engineering from Stanford University in 2003. His expertise is in the areas of networked multimedia systems, real-time voice and video communication, and low-latency media streaming over the wire-line and wireless networks. Currently holding positions at Qualcomm CDMA Technologies, San Diego, CA, he is responsible for video and multimedia system design and development for Qualcomm's mobile station modem (MSM) chipsets. From 2000 to 2001, he conducted research with Netergy Networks, Inc., Santa Clara, CA, on voice over IP systems that provide improved quality over best-effort networks. From 2001 to 2003, he had been the lead of the Stanford - Hewlett-Packard Labs low-latency video streaming project, in which he and his colleagues developed error-resilience techniques for rich media communication over IP networks at low latency. In the summer of 2002 at Hewlett-Packard Labs, Palo Alto, CA, he developed an accurate loss-distortion model for compressed video and contributed in the development of the mobile streaming media content delivery network (MSM - CDN) that delivers rich media over 3G wireless. Yi Liang received the B. Eng. degree from Tsinghua University, Beijing, China. Eric Setton received the B.S. degree from Ecole Polytechnique, Palaiseau, France in 2001 and the M.S. degree, in Electrical Engineering from Stanford University in 2003. He is currently a Ph.D. candidate in the department of Electrical Engineering of Stanford University and is part of the Image, Video and Multimedia Systems group. Multimedia communication over wired and wireless networks, video compession and image processing are his main research interests. In 2001, he received the Carnot fellowship and the SAP Stanford Graduate fellowship. In 2003, he received the Sony SNRC fellowship. He has spent time in industry in France at SAGEM and in the United States at HP labs and at Sony Electronics. He has 4 patents pending. Bernd Girod is Professor of Electrical Engineering in the Information Systems Laboratory of Stanford University, California. He also holds a courtesy appointment with the StanfordDepartment of Computer Science and he serves as Director of the Image Systems Engineering Program at Stanford. His research interests include networked media systems, video signal compression and coding, and 3-d image analysis and synthesis. He received his M.S. degree in Electrical Engineering from Georgia Institute of Technology, in 1980 and his Doctoral degree “with highest honours” from University of Hannover, Germany, in 1987. Until 1987 he was a member of the research staff at the Institut fur Theoretische Nachrichtentechnik und Informationsverarbeitung, University of Hannover, working on moving image coding, human visual perception, and information theory. In 1988, he joined Massachusetts Institute of Technology, Cambridge, MA, USA, first as a Visiting Scientist with the Research Laboratory of Electronics, then as an Assistant Professor of Media Technology at the Media Laboratory. From 1990 to 1993, he was Professor of Computer Graphics and Technical Director of the Academy of Media Arts in Cologne, Germany, jointly appointed with the Computer Science Section of Cologne University. He was a Visiting Adjunct Professor with the Digital Signal Processing Group at Georgia Institute of Technology, Atlanta, GA, USA, in 1993. From 1993 until 1999, he was Chaired Professor of Electrical Engineering/Telecommunications at University of Erlangen-Nuremberg, Germany, and the Head of the Telecommunications Institute I, co-directing the Telecommunications Laboratory. He has served as the Chairman of the Electrical Engineering Department from 1995 to 1997, and as Director of the Center of Excellence “3-D Image Analysis and Synthesis” from 1995-1999. He has been a Visiting Professor with the Information Systems Laboratory of Stanford University, Stanford, CA, during the 1997/98 academic year. As an entrepreneur, Prof. Girod has worked successfully with several start-up ventures as founder, investor, director, or advisor. Most notably, he has been a co-founder and Chief Scientist of Vivo Software, Inc., Waltham, MA (1993–98); after Vivo's aquisition, 1998-2002, Chief Scientist of RealNetworks, Inc. (Nasdaq: RNWK); and, from 1996–2004, an outside Director of 8 × 8, Inc. (Nasdaq: EGHT). Prof. Girod has authored or co-authored one major text-book, two monographs, and over 250 book chapters, journal articles and conference papers in his field, and he holds about 20 international patents. He has served as on the Editorial Boards or as Associate Editor for several journals in his field, and is currently Area Editor for Speech, Image, Video and Signal Processing of the “IEEE Transactions on Communications.” He has served on numerous conference committees, e.g., as Tutorial Chair of ICASSP-97 in Munich and ICIP-2000 in Vancouver, as General Chair of the 1998 IEEE Image and Multidimensional Signal Processing Workshop in Alpbach, Austria, and as General Chair of the Visual Communication and Image Processing Conference (VCIP) in San Jose, CA, in 2001. Prof. Girod has been a member of the IEEE Image and Multidimensional Signal Processing Committee from 1989 to 1997 and was elected Fellow of the IEEE in 1998 ‘for his contributions to the theory and practice of video communications.’ He has been named ‘Distinguished Lecturer’ for the year 2002 by the IEEE Signal Processing Society. Together with J. Eggers, he is recipient of the 2002 EURASIP Best Paper Award.     

SPS Members Receive IEEE Technical Field Awards [Society News]

The IEEE Signal Processing Society's 2010 IEEE Leon K. Kirchmayer Graduate Technical Award was presented to A.N. WIlson; the 2010 IEEE Control Systems Award was presented to G.C. Goodwin; and the 2010 IEEE James L. Flanagan Speech and Audio Processing Award was presented to S. Furui.     

Providing Throughput Guarantees in 802.11e WLAN Through a Dynamic Priority Assignment Mechanism

Supporting real-time and interactive traffic in addition to traditional data traffic with a best-effort nature represents a constantly rising need in any kind of telecommunications environment. The IEEE 802.11 based WLAN (Wireless Local Area Network) environment does not represent an exception. This is why at different protocol layers, and primarily at the MAC layer, many efforts are being put by both the research community and the standardization bodies to design effective mechanisms for user QoS (Quality of Service) differentiation. Although early results are coming into sight, such as, for example, the IEEE 802.11e standard release, still a thorough research activity is required. Aim of the present paper is to contribute to the cited research issue by proposing an improvement to the “static” traffic prioritisation mechanism foreseen by the IEEE 802.11e MAC (Medium Access Control) protocol. This latter shows a twofold drawback. First, there is no certainty that QoS requirements relevant to a given application are always fulfilled by the “statically” associated priority. Second, resource requests of the applications are not adapted to the (usually highly) variable traffic conditions of a distributed WLAN environment. The algorithm we propose is specifically tailored to “dynamically” assign 802.11e MAC priorities, depending on both application QoS requirements and observed network congestion conditions. It is carefully designed, implemented into a system simulation tool, and its highly effective behaviour assessed under variable traffic and system conditions. Antonio Iera graduated in Computer Engineering at the University of Calabria, Italy, in 1991 and received a Master Diploma in Information Technology from CEFRIEL/Politecnico di Milano, Italy, in 1992 and a Ph.D. degree from the University of Calabria, Italy, in 1996. From 1994 to 1995 he has been at the Mobile Network Division Research Center, Siemens AG Muenchen, Germany to participate to the CEC Project “RACE II 2084 ATDMA (Advanced TDMA Mobile Access)” under a “Commission of European Communities Fellowship Contract in RACE Mobility Action”. He has been with the University of Reggio Calabria, Italy, from 1997 to 2000 as Assistant Professor, and from 2001 to 2005 as Associate Professor. Currently, he is Full Professor of Telecommunications at the same University. In 1995 and in 1996 he has been the recipient of an IEEE Paper Award for the papers presented at the IEEE International Conference on Universal Personal Communications ICUPC'95, and an IEICE/IEEE Outstanding Paper Award for the paper presented at the IEEE ATM Workshop'99, respectively. He served as member of Technical Program Committees of several International Conferences, and in 2003 he has been co-Guest Editor for the special issue “QoS in Next-generation Wireless Multimedia Communications Systems” in the IEEE Wireless Communications Magazine. His research interests include QoS control and resource management in Personal Communications Systems and Enhanced Wireless and Satellite Systems. Giuseppe Ruggeri received the degree in electronics engineering from the University of Catania, Italy, in 1998. He received the Ph.D. degree in electronics, computer science and telecommunications engineering with a dissertation on “Advanced Methods to Improve the QoS in VoIP Systems Based on VBR Speech Coders”. His interests include the field of adaptive-rate voice transmission for IP Telephony applications, and support of Quality of Service in heterogeneous wireless networks and WLAN-3G interconnection-integration . He is currently Assistant Professor in the Department of Computer Science, Mathematics, Electronic and transportation systems (DIMET) at the University “Mediterranea” of Reggio Calabria. His mail address is ruggeri@ing.unirc.it. Domenico Tripodi received M.S. degree (cum laude) in electronic engeneering from the University ‘Mediterranea' of Reggio Calabria, Italy in 2003. He won a post-degree scholarship from CNIT in 2004, and he is currently at CNIT Research Unit of Reggio Calabria. His reasearch interest are in the area of QoS provisioning in Mobile Ad-Hoc Networks.     

Physical-layer air interface solutions for broadband high-speed wireless cellular systems

We propose the physical-layer (PHY) air interface solutions for downlink and uplink transmissions in broadband high-speed wireless cellular systems. A system based on low-density parity-check (LDPC) coded multiple-input-multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) time-division multiple-accessing (TDMA) (with scheduling) is proposed for downlink transmission; and a system based on orthogonal space-time block coded (STBC) multi-carrier code-division multiple-accessing (MC-CDMA) is proposed for uplink transmission. The proposed scheme can support ∼100 Mbps peak rate over 25 MHz bandwidth downlink channels and ∼30 Mbps sum rate of multiple users over 25 MHz uplink channels. Moreover, the proposed solutions provide excellent performance and reasonable complexity for mobile station and for base station. Ben Lu received the B.S. and M.S. degrees in electrical engineering from Southeast University, Nanjing, China, in 1994 and 1997; the Ph.D. degree from Texas A & M University in 2002. From 1994 to 1997, he was a Research Assistant with National Mobile Communications Research Laboratory at Southeast University, China. From 1997 to 1998, he was with the CDMA Research Department of Zhongxing Telecommunication Equipment Co., Shanghai, China. From 2002 to 2004, he worked for the project of high-speed wireless packet data transmission (4G prototype) at NEC Laboratories America, Princeton, New Jersey. He is now with Silicon Laboratories. His research interests include the signal processing and error-control coding for mobile and wireless communication systems. Xiaodong Wang received the B.S. degree in Electrical Engineering and Applied Mathematics (with the highest honor) from Shanghai Jiao Tong University, Shanghai, China, in 1992; the M.S. degree in Electrical and Computer Engineering from Purdue University in 1995; and the Ph.D degree in Electrical Engineering from Princeton University in 1998. From July 1998 to December 2001, he was an Assistant Professor in the Department of Electrical Engineering, Texas A&M University. In January 2002, he joined the faculty of the Department of Electrical Engineering, Columbia University. Dr. Wang’s research interests fall in the general areas of computing, signal processing and communications. He has worked in the areas of digital communications, digital signal processing, parallel and distributed computing, nanoelectronics and bioinformatics, and has published extensively in these areas. Among his publications is a recent book entitled “Wireless Communication Systems: Advanced Techniques for Signal Reception”, published by Prentice Hall, Upper Saddle River, in 2003. His current research interests include wireless communications, Monte Carlo-based statistical signal processing, and genomic signal processing. Dr. Wang received the 1999 NSF CAREER Award, and the 2001 IEEE Communications Society and Information Theory Society Joint Paper Award. He currently serves as an Associate Editor for the IEEE Transactions on Communications, the IEEE Transactions on Wireless Communications, the IEEE Transactions on Signal Processing, and the IEEE Transactions on Information Theory. Mohammad Madihian (S’78-M’83-SM’88-F’98) received his Ph.D in electronic engineering from Shizuoka University, Hamamatsu, Japan, in 1983. He is presently the Chief Patent Officer and Department Head, NEC Laboratories America, Inc., Princeton, New Jersey, where he conducts Microwave as well as PHY/MAC layer signal processing activities for high-speed wireless networks and personal communications applications. He holds 35 Japan/US patents and has authored/co-authored more than 130 technical publications including 25 invited talks. He has received 8 NEC Distinguished R&D Achievement Awards, the 1988 IEEE MTT-S Best Paper Microwave Prize, and 1998 IEEE Fellow Award. He has served as Guest Editor to the IEEE Journal of Solid-State Circuits, Japan IEICE Transactions on Electronics, and IEEE Transactions on Microwave Theory and Techniques. He is currently serving on the IEEE Speaker’s Bureau, IEEE Compound Semiconductor IC Symposium Executive Committee, IEEE Radio and Wireless Symposium Executive Committee, IEEE International Microwave Symposium Technical Program Committee, IEEE MTT-6 Subcommittee, IEEE MTT Editorial Board, and Technical Program Committee of International Conference on Solid State Devices and Materials. Dr. Madihian is an Adjunct Professor at Electrical and Computer Engineering Department, Drexel University, Philadelphia, Pennsylvania.     

Hardware Efficient Fast Computation of the Discrete Fourier Transform

In this paper, a new systolic array for prime N-length DFT is first proposed, and then combined with Winograd Fourier Transform algorithm (WFTA) to control the increase of the hardware cost when the transform length is large. The proposed new DFT design is both fast and hardware efficient. Compared with the recently reported DFT design with computational complexity of O(log N), the proposed design saves the average number of required multiplications by 30 to 60% and reduces the average computation time by more than 2 times, when the transform length changes from 16 to 2048. Chao Cheng received his MSEE degree from Huazhong University of Science and Technology, Wuhan, China, in 2001. With three years industrial experience as a digital communication engineer from VIA Technologies, he is now pursuing his Ph.D. degree at the University of Minnesota, Twin Cities, MN. His present research interest is in VLSI digital signal processing algorithms and their implementation. Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, and ultra wideband systems. He has published over 400 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and Signal Processing Magazine, and currently serves as the Editor-in-Chief of the IEEE Trans. on Circuits and Systems---I (2004--2005 term), and serves on the Editorial Board of the Journal of VLSI Signal Processing. He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996--1998. He is a Fellow of IEEE (1996). An erratum to this article is available at .     

Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper

There were several modulation and coding proposals for 10GBASE-T (10 Gigabit Ethernet over copper) systems. One of these is based on a 10-level pulse amplitude modulation (PAM-10) combined with a 4D (four-dimensional) 8-state trellis code similar to the one in 1000BASE-T (1000 Megabit Ethernet over copper). The trellis code can be used in a conventional manner as in 1000BASE-T, but the corresponding decoder with a long critical path needs to operate at 833 MHz. It is difficult to meet the critical path requirements of such a decoder. To solve the problem, two interleaved trellis coded modulation schemes are proposed in this paper. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than those in the conventional decoder. Thus this paper also considers the problem of complexity reduction of the decoders for the two proposed interleaved modulation schemes, and presents two novel complexity reduction schemes. Simulation results show that the error-rate performances of the two proposed interleaved schemes are quite close to that of the conventional scheme. It is also shown that the performance loss due to complexity reduction is negligible. This research was supported in part by the National Science Foundation by the grant number CCF-0429979. Yongru Gu received M.S. degree from Duke University, Durham, NC in 2001. Currently, he is working toward the Ph.D. degree at the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis. His research interests lie in high-speed low-power VLSI implementation of digital signal precessing and communication systems. Keshab K. Parhi (S'85-M'88-SM'91-F'96) received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, and ultra wideband systems. He has published over 400 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and Signal Processing Magazine, and currently serves as the Editor-in-Chief of the IEEE Trans. on Circuits and Systems - I (2004–2005 term), and serves on the Editorial Board of the Journal of VLSI Signal Processing. He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996–1998.     

Models for Architectural Power and Power Grid Noise Analysis on Data Bus

The transition activity on a data bus is a time series that determines power consumption on this data bus. The average values of power consumption and power grid voltage drop are proportional to average value of transition activity, i.e., transition probability. The fluctuation of power grid voltage drop appears as noise on power grid and its strength is determined by the second order statistics of transition activity, i.e., variance, auto-correlation function or power spectrum. In this paper, for the first time, simple accurate models for estimating variance and power spectrum of transition activity are proposed. The proposed models are based on linearly modeling spatial-time correlation of bit-level transition activity and result in low computational complexity but very good estimation accuracy. In addition, the dual bit type (DBT) [1, 2] model for estimating average transition activity was further developed. The previous DBT model was made complete with the equation derived in this paper for computing transition probability beyond breakpoint BP ₁. Besides DSP computational architecture and algorithm designs, the proposed simple models are of great significance for power grid noise decoupling and chip floor-planning. Lijun Gao (S’99–M’01) received B.E. and M.E. degrees in Communication & Electronic Systems from Tsinghua University, Beijing, China, in 1986 and 1988, respectively. He received his PhD degree in Elecrical & Computer Engineering from University of Minnesota, Minneapolis, USA, in 2001. He is also an MS degree candidate in Computer & Information Science at University of Minnesota, Minneapolis. Dr. Gao is currently with Medtronic Inc., Minneapolis, MN, and working on DSP design for pacemaker. From 2001 to 2003, he was with Bermai Inc., Minnetonka, MN and working on the design of wireless LAN (802.11a/11b) chipsets. In 2001, he worked in the R & D division of GlobeSpan Semiconductor Inc., Red Bank, NJ. From 1988 to 1991, he was a faculty member with Tsinghua University, Beijing, China. From 1991 to 1996, he was a R & D engineer with the Institute of Software, Chinese Academy of Science, Beijing, China. For the period of 1991 to 1993, he was a visiting R & D engineer at Onflo Computer Co. Hong Kong. Dr. Gao received the Science & Technology awards from the National Education Council, China, in 1994 for his contribution to radar signal processing while he was at Tsinghua University, and from the ministry of Electronic Industry, China, in 1995 for his contribution to the CJK Ideograph Unification in ISO 10646 (Unicode). His current reserach interest includes the algorithm/architecture/ circuit for VLSI design, the computational aspects of digital signal processing (DSP) and programmable DSP processor. Specifically, his focus is on the deep-submicron VLSI design, power estimation/low power design, computer arithmetic, finite field arithmetic, error control coding, cryptography, adaptive filters, equalization, beamformer, special-purpose processors and FPGA/reconfigurable computing. Keshab K. Parhi (S’85-M’88–SM’91-F’96) Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, ultra wideband systems, quantum error control coders and quantum cryptography. He has published over 350 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and currently serves on editorial board of the IEEE Signal Processing Magazine, and is the curent Editor-in-Chief of the IEEE Trans. on Circuits and Systems–I (2004–2005 term). He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996–1998. He currently serves on the Board of Governors of the IEEE Circuits and Systems Society. He was elected a Fellow of IEEE in 1996.     

Extremely-Wide-Range Supply-Independent CMOS Voltage References for Telemetry-Powering Applications

This paper reports a voltage reference circuit in standard CMOS process. It exhibits excellent supply independency for a wide input voltage range, which is of great importance in telemetry-powered systems. This circuit is based on the well-known V_GS-reference supply-independent current reference circuit, but it is designed to serve as a voltage reference. While the reference current generated by this circuit varies with the supply voltage, a self-compensating mechanism can be found in voltage-mode operation of the circuit that results in a supply-independent reference voltage. This supply independency is well observed in the static operation of the circuit over an extremely wide input range, as well as in its dynamic behavior for high frequency ripples on the input voltage. Based on the proposed idea, a multi-output voltage reference and a CMOS DC level shifter are also designed. The proposed voltage reference circuits have been fabricated using MOSIS 1.6 μm standard CMOS process. The basic voltage reference provides 957 μV/V static supply dependency, rejects input ripples of up to 8 MHz by 60± 3dB, and consumes only 15.8–36.9 μA when the input voltage varies in the range 2.6–12 V. Amir M. Sodagar received the B.S. degree from K.N. Toosi (KNT) University of Technology, Tehran, Iran, and M.S. and Ph.D. degrees from Iran University of Science & Technology (IUST), Tehran, Iran all in Electrical Engineering in 1992, 1995, and 2000, respectively. From 1992 to 2000 he was with S. Rajaee University as a Lecturer. After receiving the Ph.D. degree until 2002 he was with the NSF Engineering Research Center for Wireless Integrated Micro Systems (WIMS), Electrical Engineering & Computer Science (EECS) Dept., University of Michigan as a Post-Doctoral Research Fellow. From 2002 to 2004 he was with S. Rajaee University and KNT University of Technology as an Assistant Professor and an Adjunct Professor, respectively, and since 2004 he has been with the University of Michigan as an Associate Visiting Research Scientist. Dr. Sodagar was known as the Outstanding Electrical Engineering Graduate Student of the IUST in 1995, and receiv ed the IUST's Best Ph.D. Research Achievement Award in 2000. He was also the recipient of S. Rajaee University's Distinguished Faculty Member Award for “1998–1999” and “1999–2000” academic years, and S. Rajaee University's Distinguished Researcher Award for “2002–2003” academic year. He was involved in the design of integrated circuits in collaboration with the Center for Semiconductor Research and Fabrication from 1994 to 1995, VLSI Circuits & Systems Laboratory at the University of Tehran from 1997 to 1998, and EMAD Semicon Company from 1998 to 2000. He has authored one book, authored/co-authored more than 20 journal and conference papers, and served as the technical paper reviewer for several IEEE journals/transactions and also conferences. Dr. Sodagar's research interests are generally in the field of mixed-signal integrated circuit design, and focused on: integrated circuits for neural recording & stimulation, telemetry powering and control of implantable microsystems, frequency synthesizers, analog building blocks, and transistor-level implementations of digital logic families. Khalil Najafi (IEEE S '84, M '86, SM '97, F'00) received the B.S., M.S., and the Ph.D. degree in 1980, 1981, and 1986 respectively, all in Electrical Engineering from the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. From 1986–1988 he was employed as a Research Fellow, from 1988–1990 as an Assistant Research Scientist, from 1990–1993 as an Assistant Professor, from 1993–1998 as an Associate Professor, and since September 1998 as a Professor and the Director of the Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan. His research interests include: micromachining technologies, micromachined sensors, actuators, and MEMS; analog integrated circuits; implantable biomedical microsystems; micropackaging; and low-power wireless sensing/actuating systems. Dr. Najafi was awarded a National Science Foundation Young Investigator Award from 1992–1997, was the recipient of the Beatrice Winner Award for Editorial Excellence at the 1986 International Solid-State Circuits Conference, of the Paul Rappaport Award for co-authoring the Best Paper published in the IEEE Transactions on Electron Devices, and of the Best Paper Award at ISSCC 1999. In 2003 he received the EECS Outstanding Achievement Award, in 2001 he received the Faculty recognition Award, and in 1994 the University of Michigan's “Henry Russel Award” for outstanding achievement and scholarship, and was selected as the “Professor of the Year” in 1993. In 1998 he was named the Arhtur F. Thurnau Professor for outstanding contributions to teaching and research, and received the College of Engineering's Research Excellence Award. He has been active in the field of solid-state sensors and actuators for more than twenty years, and has been involved in several conferences and workshops dealing with solid-state sensors and actuators, including the International Conference on Solid-State Sensors and Actuators, the Hilton-Head Solid-State Sensors and Actuators Workshop, and the IEEE/ASME Micro Electromechanical Systems (MEMS) Conference. Dr. Najafi is the Editor for Solid-State Sensors for IEEE Transactions on Electron Devices, an Associate Editor for the Journal of Micromechanics and Microengineering, Institute of Physics Publishing, and an editor for the Journal of Sensors and Materials. He also served as the Associate Editor for IEEE Journal of Solid-State Circuits from 2000–2004, and the associate editor for IEEE Trans. Biomedical Engineering from 1999–2000. He is a Fellow of the IEEE.     

DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation

To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations. Seok-Bae Park received the B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Ohio State University, Columbus, Ohio. He is currently with Firstpass Technologies, Inc., Dublin, Ohio as a Senior RF and Mixed-Signal Design Engineer. His current interests include low voltage/low power CMOS RF/analog/mixed-signal integrated circuits and systems for wireless communications. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is Professor and The Founding Director of the Analog VLSI Lab, The Ohio State University. He advised the work of 40 PhD students and of 85 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has coedited and coauthored several books including a text on Analog VLSI Signal and Information Processing, McGraw Hill. His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Firstpass Technologies Inc., a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

Statistical Multiplexing based on MPEG-4 Fine Granularity Scalability Coding

Conventional statistical multiplexing methods for MPEG-1/2 programs involve high computationally complex transcoding (decoding and re-encoding) process to convert the original bit-rate into the target bit-rate. To avoid a time-consuming transcoding process, a new statistical multiplexer is proposed to enable content provider to easily convert the bit-rates by exploiting the MPEG-4 fine granularity scalability (FGS) coding scheme. The proposed statistical multiplexer is particularly useful for multiple-program broadcasting applications, including Internet television and video on demand, as well as value-added MPEG-4 video streaming services for DVB and ATSC digital TV systems. The proposed multiplexer mainly includes two parts: the FGS-based frame lag scheme and the optimal bit-plane truncation scheme. The FGS-based frame lag scheme exploits intra- and inter-layer correlations exist in MPEG-4 FGS bit-streams. The optimal bit-plane truncation scheme dynamically truncates enhancement layers of FGS bit-streams under the available bandwidth constraint and the quality/smoothness constraint. Experimental results show that high statistical multiplexing efficiency, inter-program fairness, and intra-program smoothness are achieved by the proposed multiplexer. Portion of this work was presented at Third International Workshop on Digital and Computational Video (DCV2003), USA, November 2002. Xiaokang Yang received B.S. degree from Xiamen University, Xiamen, China, in 1994, M.Eng. degree from the Chinese Academy of Sciences, Shanghai, China, in 1997, and the Ph.D. degree from Shanghai Jiao Tong University, Shanghai, China, in 2000. From September 2000 to March 2002, he worked as a Research Fellow at the Centre for Signal Processing, Nanyang Technological University, Singapore. From April 2002 to October 2004, he was a Research Scientist with the Institute for Infocomm Research (I²R), Singapore. He is currently an Associate Professor of the Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China. His current research interests include scalable video coding, perceptual video processing, video transmission over networks, and digital television. He has published over 60 refereed papers and filed six patents. He is currently a member of Visual Signal Processing and Communications Technical Committee of the IEEE Circuits and Systems Society. He has received awards from A-STAR and Tan Kah Kee foundations (Singapore), and the Best Young Investigator Paper Award at IS&T/SPIE International Conference on Video Communication and Image Processing (VCIP'2003) in perceptual video processing. Nam Ling received a B.Eng. degree in Electrical Engineering from Singapore. He received M.S. and Ph.D. degrees, both in Computer Engineering, from the University of Louisiana at Lafayette, Louisiana, U.S.A. Prof. Ling is currently a full Professor with the Department of Computer Engineering and the Associate Dean (Graduate Studies and Research) for the School of Engineering at Santa Clara University (SCU), California, U.S.A. Prof. Ling is also a Consulting Professor and Honorary Advisor to the National University of Singapore. Prof. Ling has over 120 publications in the fields of video coding, decoder design, video streaming, and systolic arrays. He is the primary author of the book entitled Specification and Verification of Systolic Arrays. Prof. Ling received the Arthur Vining Davis Junior Faculty Fellowship in 1991 and the SCU Outstanding Achievement Award in Teaching, Research, and Service, in 1992. Prof. Ling was named 1999 Researcher of the Year by SCU Engineering. He received the SCU Award for Recent Achievement in Scholarship in 2002 and the President's Special Recognition Award in 2005. He was named IEEE Distinguished Lecturer (Circuits and Systems) for the year 2002-2003. Prof. Ling also received the 2003 IEEE ICCE Best Paper Award. His co-authored fast motion estimation method was adopted into the MPEG/VCEG JVT video international standard in 2005. Prof. Ling served as an Associate Editor for the IEEE Transactions on Circuits and Systems--I in 2002--03. He is currently a Guest Co-editor for the Journal of VLSI Signal Processing Systems. In 1993--1995, Prof. Ling served as the Chair of the IEEE Computer Society Technical Committee (TC) on Microprocessors and Microcomputers. Currently he serves as the Chair-elect for the CASCOM TC (IEEE CAS Society). He is a member in the VSPC TC (IEEE CAS Society) and the DISPS TC (IEEE SP Society). Prof. Ling was the General Chair of the IEEE Hot Chips Symposium in 1995. He served as Program Chair for DCV'02 and SiPS'00. He has been a Track Co-Chair for ISCAS since 2004. Prof. Ling served in program committees, organizing committees, and as session chairs for many IEEE conferences. He holds professional memberships in IEEE, SPIE, and ASEE.     

Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters

There are many applications in which particle filters outperform traditional signal processing algorithms. Some of these applications include tracking, joint detection and estimation in wireless communication, and computer vision. However, particle filters are not used in practice for these applications mainly because they cannot satisfy real-time requirements. This paper presents an efficient resampling architecture for parallel particle filtering. The proposed architecture is flexible such that it supports various modes of parallel resampling operations with up to four processing elements. The resampling algorithm is developed in order to compensate for possible error caused by finite precision quantization in the resampling step. Communication between the processing elements after resampling is identified as an implementation bottleneck, and therefore, concurrent buffering is incorporated in order to speed up communication of particles among processing elements. The flexible resampling mechanism is implemented in 0.35 μ m CMOS process and its complexity and performance are analyzed. Sangjin Hong received the B.S and M.S degrees in EECS from the University of California, Berkeley. He received his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at State University of New York, Stony Brook. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power VLSI design of multimedia wireless communications and digital signal processing systems, reconfigurable SoC design and optimization, VLSI signal processing, and low-complexity digital circuits. Prof. Hong served on numerous Technical Program Committees for IEEE conferences. Prof. Hong is a Senior Member of IEEE. Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University – State University of New York in 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems. Miodrag Bolić received the B.S. and M.S. degrees in electrical engineering from the University of Belgrade, Yugoslavia, in 1996 and 2001, respectively, and his Ph.D. degree in electrical engineering from Stony Brook University, NY, USA. He is currently with the School of Information Technology and Engineering at the University of Ottawa, Canada. From 1996 to 2000 he was Research Associate with the Institute of Nuclear Science Vinĉa, Yugoslavia. From 2001 to 2004 he worked part-time at Symbol Technologies Inc., NY, USA. His research is related to VLSI architectures for digital signal processing and signal processing in wireless communications and tracking. Petar M. Djurić received his B.S. and M.S. degrees in electrical engineering from the University of Belgrade, in 1981 and 1986, respectively, and his Ph.D. degree in electrical engineering from the University of Rhode Island, in 1990. From 1981 to 1986 he was Research Associate with the Institute of Nuclear Sciences, Vinĉa, Belgrade. Since 1990 he has been with Stony Brook University, where he is Professor in the Department of Electrical and Computer Engineering. He works in the area of statistical signal processing, and his primary interests are in the theory of modeling, detection, estimation, and time series analysis and its application to a wide variety of disciplines including wireless communications and bio-medicine. Prof. Djurić has served on numerous Technical Committees for the IEEE and SPIE and has been invited to lecture at universities in the US and overseas. He is the Area Editor of Special Issues of the Signal Processing Magazine, the Treasurer of the IEEE Signal Processing Conference Board, and Associate Editor of the IEEE Transactions on Signal Processing. He is also the Chair elect of the IEEE Signal Processing Society Committee on Signal Processing—Theory and Methods, and an Editorial Board member of Digital Signal Processing, the EURASIP Journal on Applied Signal Processing and the EURASIP Journal on Wireless Communications and Networking. Prof. Djurić is a Member of the American Statistical Association and the International Society for Bayesian Analysis.     

Energy efficient node-to-node authentication and communication confidentiality in wireless sensor networks

A distributed Wireless Sensor Network (WSN) is a collection of low-end devices with wireless message exchange capabilities. Due to the scarcity of hardware resources, the lack of network infrastructures, and the threats to security, implementing secure pair-wise communications among any pair of sensors is a challenging problem in distributed WSNs. In particular, memory and energy consumption as well as resilience to sensor physical compromise are the most stringent requirements. In this paper, we introduce a new threat model to communications confidentiality in WSNs, the smart attacker model. Under this new, more realistic model, the security features of previously proposed schemes decrease drastically. We then describe a novel pseudo-random key pre-deployment strategy ESP that combines all the following properties: (a) it supports an energy-efficient key discovery phase requiring no communications; (b) it provides node to node authentication; (c) it is highly resistant to the smart attacker.We provide both asymptotic results and extensive simulations of the schemes that are beingproposed. This work was partially funded by the WEB-MINDS project supported by the Italian MIUR under the FIRB program, and by the PRIN 2003 “Web-based Management and Representation of Spatial and Geographic Data” program from the Italian MIUR. Roberto Di Pietro is partially funded by ISTI-CNR, WNLab, Pisa, with a Post-doc grant under the IS-MANET program. Roberto Di Pietro received the Ph.D. in Computer Science from the University of Roma “La Sapienza”, Italy, in 2004. He received the Bs. and Ms. degree in Computer Science from the University of Pisa, Italy, in 1994. Since 1995 he has been working for the technical branch of the Italian Army and the Internal Affairs Ministry. His main research interests include: security for mobile ad hoc and wireless networks, security for distributed systems, secure multicast, applied cryptography and computer forensics. Luigi V. Mancini received the PhD degre in Computer Science from the University of Newcastle upon Tyne, UK, in 1989, and the Laurea degree in Computer Science from the University of Pisa, Italy, in 1983. From 2000, he is a full professor of Computer Science at the Dipartimento di Informatica of the University of Rome “La Sapienza”. Since 1994, he is a visiting research professor of the Center for Secure Information Systems, GMU, Virginia, USA. Currently he is the advisor of six Ph.D students. His current research interests include: computer network and information security, wireless network security, fault-tolerant distributed systems, large-scale peer-to-peer systems, and hard-real-time distributed systems. He published more than 60 scientific papers in international conferences and journals such as: ACM TISSEC, IEEE TKDE, IEEE TPDS, and IEEE TSE. He served in the program committees of several international conferences which include: ACM Conference on Computer and Communication Security, ACM Conference on Conceptual Modeling, ACM Symposium on Access Control Models and Technology, ACM Workshop of Security of Ad-hoc and Sensor Networks, IEEE Securecomm, IEEE Conference on Cluster Computing. He is also the program chair of the first two editions of the IEEE Workshop on Hot Topics in Peer-to-Peer Systems held in 2004 (Volendam, Holand) and in 2005 (San Diego, California). Currently, he is a member of the Scientific Board of the Italian Communication Police force, and the director of the Master degree program in Computer and Network Security of the University of Rome “La Sapienza”, Italy. Alessandro Mei received the Laurea degree in computer science from the University of Pisa, Italy, in 1994, and the PhD degree in mathematics from the University of Trento, Italy, in 1999. In 1998, he was at the Department of EE-Systems of the University of Southern California, Los Angeles, as a visiting scholar for one year. After holding a postdoctoral position at the University of Trento, in 2001 he joined the Faculty of Science of the University of Rome "La Sapienza", Italy, as an assistant professor of computer science. His main research interests include security of distributed systems and networks, algorithms for parallel, distributed, and optical systems and reconfigurable computing. He was presented with the Best Paper Award of the 16th IEEE International Parallel and Distributed Processing Symposium in 2002, the EE-Systems Outstanding Research Paper Award of the University of Southern California for 2000, and the Outstanding Paper Award of the Fifth IEEE/ACM International Conference on High Performance Computing in 1998. He is a member of the ACM and the IEEE and, from 2005, he is an Associate Editor of IEEE Transactions on Computers.     

A digital calibration algorithm for implementing accurate on-chip resistors

A digital calibration algorithm that provides a systematic method for implementing accurate integrated resistors without compromising linearity or noise performance is described. The technique uses a single external resistor as a reference to implement multiple, different valued integrated resistors without requiring any accurate reference voltage. The algorithm provides a method to calibrate several on-chip resistors without replicating the calibration circuit, and it can achieve an arbitrary accuracy limited only by the external resistor’s accuracy and mismatch errors. Terminations for two high speed wire line transceivers are implemented using the algorithm and simulations and measurements results show adequate performance across process, temperature, and supply voltage. Ayman A. Fayed was born Egypt, in 1975. He received the B.Sc. degree from the Electronics and Communications Department, Cairo University, Cairo, Egypt in 1998, and the M.Sc. and Ph.D. degrees from The Ohio State University, Columbus, in 2000 and 2004 respectively. Since 2002, he has been with Texas Instruments Inc. as an analog and mixed-signal circuit designer. He has been a key contributor to TI#x2019;s high-speed wire line transceivers product line. He has been awarded two US patents in the field. His research interests include mixed-signal CMOS circuit design for high-speed wire line transceivers, adaptive equalization, and power management systems. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the Far East. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has co-edited and coauthored several books including a text on Analog VLSI Signal and Information Processing, (McGraw Hill). His last book (2004) is entitled CMOS PLLs and VCOs for 4G wireless, Springer. He co-founded ANACAD Egypt (now part of Mentor Graphics, Inc.) and Spirea AB, Stockholm (now Firstpass Semiconductors AB), a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He is a Fellow of IEEE. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada.     

基于Pd的“语音信号处理”教学探索

本文将实时的图形编程语言Pd引入“语音信号处理”课程的教学中.笔者介绍了Pd的编程要素,并结合语音信号处理实例说明Pd的简易编程方法,列出Pd在“语音信号处理”教学中的应用,通过语音生成实验说明它具有较强的实时交互性,可以让学生从视听两方面感受参数变化带来的影响.这有助于将抽象的概念形象化,促进学生深刻理解理论,提高教学质量.     

A Study of Shadowing on Indoor Visible-Light Wireless Communication Utilizing Plural White LED Lightings

White LED is considered as a strong candidate for the future lighting technology. We have proposed an optical wireless communication system that employs white LEDs for indoor wireless networks. In this system, LED is used not only as a lighting device, but also as a communication device. The transmitter has large optical power and large emission characteristics to function as lighting device. And the system has specific wireless channel impulse response differing from infrared wireless communication. In this paper, we discuss about shadowing effect on the system utilizing plural LED lightings including the performance of ISI based on the impulse response. We consider the downlink transmission based on TDMA and evaluate the shadowing effect caused by pedestrians with computer simulation. When the shadowing often occurs at 800 Mb/s, the performance of outage call duration rate and blocking rate are improved by using 3 LED lightings compared with 1 or 2 LED lightings. And, we show that the system with the optimal number of the LED lighting is robust against shadowing and can accommodate more calls. Toshihiko Komine was born in Shizuoka, Japan, on November 17, 1978. He received the B.E. and M.E. degrees in Information and Computer Science from Keio University, Yokohama, Japan, in 2001 and 2003 respectively. He is currently studying for the Ph.D. degree at Department of Information and Computer Science, Keio University. His current research interests are optical wireless communications and LED communications. Shinichiro Haruyama is a professor at Department of Information and Computer Science, Faculty of Science and Technology, Keio University, Yokohama, Japan. He received an M.S. in engineering science from University of California at Berkeley in 1983 and a Ph.D. in computer science from the University of Texas at Austin in 1990. He worked for Bell Laboratories of AT{&}T and Lucent Technologies, U.S.A from 1991 to 1996, and for Sony Computer Science Laboratories, Inc. from 1998 to 2002. His research interests include reconfigurable system, system design automation, wireless communication, and visible light communication. Masao Nakagawa was born in Tokyo, Japan in 1946. He received the B.E., M.E. and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1969, 1971 and 1974 respectively. Since 1973, he has been with the Department of Electrical Engineering, Keio University, where he is now a Professor. His research interests are in CDMA, consumer Communications, Mobile communications, ITS (Intelligent Transport Systems), Wireless Home Networks, and Visible light Communication. He received 1989 IEEE Consumer Electronics Society Paper Award, 1999-Fall Best Paper Award in IEEE VTC, IEICE Achievement Award in 2000, IEICE Fellow Award in 2001. He was the executive committee chairman on International Symposium on Spread Spectrum Techniques and Applications in 1992 and the technical program committee chairman of ISITA (International Symposium on Spread Spectrum Techniques and Applications) in 1994. He is an editor of Wireless Personal Communications and was a guest editor of the special issues on “CDMA Networks I, II, III and IV” published in IEEE JSAC in 1994 (I and II) and 1996 (III and IV). He chairs the Wireless Home Link sub-committee in MMAC (Multimedia Mobile Access Communication Promotion Committee).     

A Credit-Based On-Demand QoS Routing Protocol Over Bluetooth WPANs

The quality-of-service (QoS) communication that supports mobile applications to guarantee bandwidth utilization is an important issue for Bluetooth wireless personal area networks (WPANs). In this paper, we address the problem of on-demand QoS routing with interpiconet scheduling in Bluetooth WPANs. A credit-based QoS (CQ) routing protocol is developed which considers different Bluetooth packet types, because different types of Bluetooth packets have different bandwidth utilization levels. This work improves the bandwidth utilization of Bluetooth scatternets by providing a new interpiconet scheduling scheme. This paper mainly proposes a centralized algorithm to improve the bandwidth utilization for the on-demand QoS routing protocol. The centralized algorithm incurs the scalability problem. To alleviate the scalability problem, a distributed algorithm is also investigated in this work. The performance analysis illustrates that our credit-based QoS routing protocol achieves enhanced performance compared to existing QoS routing protocols.This work was supported by the National Science Council of the Republic of China under grant nos. NSC-92-2213-E-194-022 and NSC-93-2213-E-194-028. Yuh-Shyan Chen received the B.S. degree in computer science from Tamkang University, Taiwan, Republic of China, in June 1988 and the M.S. and Ph.D. degrees in Computer Science and Information Engineering from the National Central University, Taiwan, Republic of China, in June 1991 and January 1996, respectively. He joined the faculty of Department of Computer Science and Information Engineering at Chung-Hua University, Taiwan, Republic of China, as an associate professor in February 1996. He joined the Department of Statistic, National Taipei University in August 2000, and joined the Department of Computer Science and Information Engineering, National Chung Cheng University in August 2002. Dr. Chen served as Co-Editors-in-Chief of International Journal of Ad Hoc and Ubiquitous Computing (IJAHUC), Editorial Board Member of Telecommunication System Journal, International Journal of Internet Protocol Technology (IJIPT) and The Journal of Information, Technology and Society (JITAS). He also served as Guest Editor of Telecommunication Systems, special issue on “Wireless Sensor Networks” (2004), and Guest Editor of Journal of Internet Technology, special issue on “Wireless Internet Applications and Systems” (2002) and special issue on “Wireless Ad Hoc Network and Sensor Networks” (2004). He was a Vice Co-Chair, Wireless IP Symposium of WirelressCOM2005, USA (2005) and a Workshop Co-Chair of the 2001 Mobile Computing Workshop, Taiwan. Dr. Chen also served as IASTED Technical Committee on Telecommunications for 2002–2005, WSEAS International Scientific Committee Member (from 2004), Program Committee Member of IEEE ICPP'2003, IEEE ICDCS'2004, IEEE ICPADS'2001, ICCCN'2001–2005, MSN'2005, IASTED CCN'2002–2005, IASTED CSA'2004–2005, IASTED NCS'2005, and MSEAT'2003–2005. His paper wins the 2001 IEEE 15th ICOIN-15 Best Paper Award. Dr. Chen was a recipient of the 2005 Young Scholar Research Award given by National Chung Cheng University to four young faculty members, 2005. His recent research topics include mobile ad-hoc network, wireless sensor network, mobile learning system, and 4G system. Dr. Chen is a member of the IEEE Computer Society, IEICE Society, and Phi Tau Phi Society. Keng-Shau Liu received the M.S. degree in Computer Science and Information Engineering from National Chung Cheng University, Taiwan, Republic of China, in July 2004. His research includes wireless LAN, Bluetooth, and mobile learning.