A fast-settling charge-pump PLL with constant loop bandwidth

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the \(\Delta \varSigma\) modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump \(Icp\) is programmed not only to compensate the variation of voltage-controlled oscillator gain \(Kvco\), but also for adapting to the change of divider ratio \(N_{m}\). This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 µm CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is ? 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized \(\left( {Icp*Kvco} \right)/N_{m}\) which is equivalent to the variation of PLL loop bandwidth ranges from ? 6 to 6%.     

Experimental implementation of $$\Delta \Sigma $$AD modulator with dynamic analog components

This paper presents an experimental prototype of 2nd-order multi-bit \(\Delta \Sigma \)AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential \(-1\) dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.     

IGCC for PAPR Reduction in OFDM Systems Over the Nonlinearity of SSPA and Wireless Fading Channels

High peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems seriously impacts power efficiency in radio frequency section due to the nonlinearity of high-power amplifiers. In this article, an improved gamma correction companding (IGCC) is proposed for PAPR reduction and investigated under multipath fading channels. It is shown that the proposed IGCC provides a significant PAPR reduction while improving power spectral levels and error performances when compared with the previous gamma correction companding. IGCC outperforms existing companding methods when a nonlinear solid-state power amplifier (SSPA) is considered. Additionally, with the introduction of \(\alpha , \beta , \gamma \), and \(\varDelta \) parameters, the improved companding can offer more flexibility in the PAPR reduction and therefore achieves a better trade-off among the PAPR gain, bit error rate (BER), and power spectral density (PSD) performance. Moreover, IGCC improves the BER and PSD performances by minimizing the nonlinear companding distortion. Further, IGCC improves signal-to-noise ratio (SNR) degradation (\(\varDelta _{\mathrm{SNR}}\)) and total degradation performances by 12.2 and 12.8 dB, respectively, considering an SSPA with input power back-off of 3.0 dB. Computer simulation reveals that the performances of IGCC are independent of the modulation schemes and works with arbitrary number of subcarriers (N), while it does not increase computational complexity when compared with the existing companding schemes used for PAPR reduction in OFDM systems.     

Minmax-concave total variation denoising

Total variation (TV) denoising is a commonly used method for recovering 1-D signal or 2-D image from additive white Gaussian noise observation. In this paper, we define the Moreau enhanced function of \(L_1\) norm as \({\varPhi }_\alpha (x)\) and introduce the minmax-concave TV (MCTV) in the form of \({\varPhi }_\alpha (Dx)\), where D is the finite difference operator. We present that MCTV approaches \(\Vert Dx\Vert _0\) if the non-convexity parameter \(\alpha \) is chosen properly and apply it to denoising problem. MCTV can strongly induce the signal sparsity in gradient domain, and moreover, its form allows us to develop corresponding fast optimization algorithms. We also prove that although this regularization term is non-convex, the cost function can maintain convexity by specifying \(\alpha \) in a proper range. Experimental results demonstrate the effectiveness of MCTV for both 1-D signal and 2-D image denoising.     

High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications

This paper presents a new time-mode duty-cycle-modulation-based high-accuracy temperature sensor. Different from the well-known \({\varSigma }{\varDelta }\) ADC-based readout structure, this temperature sensor utilizes a temperature-dependent oscillator to convert the temperature information into temperature-related time-mode parameter values. The useful output information of the oscillator is the duty cycle, not the absolute frequency. In this way, this time-mode duty-cycle-modulation-based temperature sensor has superior performance over the conventional inverter-chain-based time domain types. With a linear formula, the duty-cycle output streams can be converted into temperature values. The design is verified in 65nm standard digital CMOS process. The verification results show that the worst temperature inaccuracy is kept within 1\(\,^{\circ }\mathrm{C}\) with a one-point calibration from \(-\)55 to 125 \(^{\circ }\mathrm{C}\). At room temperature, the average current consumption is only 0.8 \(\upmu \)A (1.1\(\,\upmu \)A in one phase and 0.5 \(\upmu \)A in the other) with 1.2 V supply voltage, and the total energy consumption for a complete measurement is only 0.384 \({\hbox {nJ}}\).     

Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance

In this paper, a novel, high-performance and robust sense amplifier (SA) design is presented for small \(I_\mathrm{CELLl}\) SRAM, using fin-shaped field effect transistors (FinFET) in 22-nm technology. The technique offers data-line-isolated current sensing approach. Compared with the conventional CSA (CCSA) and hybrid SA (HSA), the proposed current feed-SA (CF-SA) demonstrates 2.15\(\times \) and 3.02\(\times \) higher differential current, respectively, for \({V}_{\mathrm{DD}}\) of 0.6 V. Our results indicate that even at the worst corner, CF-SA can provide 2.23\(\times \) and 1.7\(\times \) higher data-line differential voltage compared with CCSA and HSA, respectively. Further, 66.89 and 31.47 % reductions in the cell access time are achieved compared to the CCSA and HSA, respectively, under similar \(I_\mathrm{CELLl}\) and bit-line and data-line capacitance. Statistical simulations have proved that the CF-SA provides high read yield with 32.39 and 22.24 % less \(\upsigma _{\mathrm{Delay}}\). It also offers a much better read effectiveness and robustness against the data-line capacitance as well as \({V}_{\mathrm{DD}}\) variation. Furthermore, the CF-SA is able to tolerate a large offset of the input devices, up to 80 mV at \({V}_{\mathrm{DD}}=0.6\hbox {V}\).     

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.     

A unified framework for performance evaluation over generalized fading channels

In this paper, we present a unified framework to analyze the performance of the average bit error probability (BEP) and the outage probability over generalized fading channels. Specifically, we assume that the probability density function (PDF) of the instantaneous signal-to-noise ratio \(\zeta \) is given by the product of: power function, exponential function, and the modified Bessel function of the first kind, i.e., \(f_{\zeta }(\zeta )=\zeta ^{\lambda -1}exp\left( -a\zeta ^{\beta }\right) I_{v}\left( b\zeta ^{\beta }\right) \). Based on this PDF, we obtain a novel closed-form expression for the average BEP over such channels perturbed by an additive white generalized Gaussian noise (AWGGN). Note that other well-known noise types can be deduced from the AWGGN as special cases such as Gaussian noise, Laplacian noise, and impulsive noise. Furthermore, we obtain a novel closed-form expression for the outage probability. As an example of such channels, and without loss of generality, we analyze the performance of the average BEP and the outage probability over the \(\eta \)–\(\mu \) fading channels. Analytical results accompanied with Monte-Carlo simulations are provided to validate our analysis.     

All-digital gated ring oscillator $$\Delta \Sigma$$ modulators

This paper presents all-digital time-mode \(\Delta \Sigma\) modulators. The proposed modulators consist of a voltage-to-time integrator, a seven-stage gated ring oscillator functioning as a 3-bit quantizer, and seven digital differentiators. A detailed analysis of the nonlinear characteristics of the modulators is provided. Designed in IBM 130 nm 1.2 V CMOS technology with a 100 mV 100 kHz sinusoidal input and a 4.4 MHz frequency clock, the first-order modulator provides 47 dB SNR over 0–150 KHz bandwidth while consuming 1.1 mW while the second-order modulator provides 55 dB SNR over the same bandwidth while consuming consumes 1.45 mW.     

An Adaptive Radial Basis Function Neural Network Filter for Noise Reduction in Biomedical Recordings

Electroencephalogram (EEG) recordings often experience interference by different kinds of noise, including white, muscle and baseline, severely limiting its utility. Artificial neural networks (ANNs) are effective and powerful tools for removing interference from EEGs. Several methods have been developed, but ANNs appear to be the most effective for reducing muscle and baseline contamination, especially when the contamination is greater in amplitude than the brain signal. An ANN as a filter for EEG recordings is proposed in this paper, developing a novel framework for investigating and comparing the relative performance of an ANN incorporating real EEG recordings. This method is based on a higher-order statistics-based radial basis function (RBF) network. This ANN improves the results obtained with the conventional EEG filtering techniques: wavelet, singular value decomposition, principal component analysis, adaptive filtering and independent components analysis. Average results for the RBF-based method provided a noise reduction (SIR) of (mean\(\pm \) SD) \(\mathrm{SIR}=19.3\pm 0.3\) in contrast to traditional compared methods that, for the best case, yielded \(\mathrm{SIR}=15.2\pm 0.3\). The system has been evaluated within a wide range of EEG signals. The present study introduces a new method of reducing all EEG interference signals in one step with low EEG distortion and high noise reduction.     

Design-to-testing: a low-power, 1.25 GHz,single-bit single-loop continuous-time $$\Delta \Sigma$$ modulator with 15 MHz bandwidth and 60 dB dynamic range

Continuous-time Delta-Sigma (CT-\(\Delta \Sigma\)) analog-to-digital converters have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths >15 MHz and higher resolution of 10–14 bits. This paper presents the complete design-to-testing tutorial of a state-of-the-art high-speed single-bit CT-\(\Delta \Sigma\) architecture and its circuit design details in 0.13 μm CMOS technology node sampling at 1.25 GS/s. The designed modulator achieves higher dynamic range of 60 dB in a wide conversion bandwidth of 15 MHz and consumes only 3.5 mW. The proposed modulator achieves a Figure of Merit of 154 fJ/level.     

The first constant factor approximation for minimum partial connected dominating set problem in growth-bounded graphs

The idea of virtual backbone has emerged to improve the efficiency of flooding based routing algorithms for wireless networks. The effectiveness of virtual backbone can be improved as its size decreases. The minimum connected dominating set (CDS) problem was used to compute minimum size virtual backbone. However, as this formulation requires the virtual backbone nodes to connect all other nodes, even the size of minimum virtual backbone can be large. This observation leads to consider the minimum partial CDS problem, whose goal is to compute a CDS serving only more than a certain portion of the nodes in a given network. So far, the performance ratio of the best approximation algorithm for the problem is \(O(\ln \varDelta ),\) where \(\varDelta\) is the maximum degree of the input general graph. In this paper, we first assume the input graph is a growth-bounded graph and introduce the first constant factor approximation for the problem. Later, we show that our algorithm is an approximation for the problem in unit disk graph with a much smaller performance ratio, which is of practical interest since unit disk graph is popular to abstract homogeneous wireless networks. Finally, we conduct simulations to evaluate the average performance of our algorithm.     

Stabilization of Discrete-time Fuzzy Systems Via Delta Operators and its Application to Truck–Trailer Model

This paper addresses the problem of robust \(L_2{-}L_\infty \) control in delta domain for a class of Takagi–Sugeno (TS) fuzzy systems with interval time-varying delays and disturbance input. In particular, the system under study involves state time delay, uncertainties and fast sampling period \(\mathcal {T}\). The main aim of this work was to design a \(L_2{-}L_\infty \) controller such that the proposed TS fuzzy system is robustly asymptotically stable with a \(L_2{-}L_\infty \) prescribed performance level \(\gamma >0\). Based on the proper Lyapunov–Krasovskii functional (LKF) involving lower and upper bound of time delay and free-weighting technique, a new set of delay-dependent sufficient conditions in terms of linear matrix inequalities (LMIs) are established for obtaining the required result. The result reveals that the asymptotic stability is achieved quickly when the sampling frequency is high. Finally, a numerical example based on the truck–trailer model is given to demonstrate the effectiveness and potential of the proposed design technique.     

A novel optimized neutrosophic <Emphasis Type="Italic">k</Emphasis>-means using genetic algorithm for skin lesion detection in dermoscopy images

This paper implemented a new skin lesion detection method based on the genetic algorithm (GA) for optimizing the neutrosophic set (NS) operation to reduce the indeterminacy on the dermoscopy images. Then, k-means clustering is applied to segment the skin lesion regions. Therefore, the proposed method is called optimized neutrosophic k-means (ONKM). On the training images set, an initial value of \(\alpha \) in the \(\alpha \)-mean operation of the NS is used with the GA to determine the optimized \(\alpha \) value. The Jaccard index is used as the fitness function during the optimization process. The GA found the optimal \(\alpha \) in the \(\alpha \)-mean operation as \(\alpha _{\mathrm{optimal}} =0.0014\) in the NS, which achieved the best performance using five fold cross-validation. Afterward, the dermoscopy images are transformed into the neutrosophic domain via three memberships, namely true, indeterminate, and false, using \(\alpha _{\mathrm{optimal}}\). The proposed ONKM method is carried out to segment the dermoscopy images. Different random subsets of 50 images from the ISIC 2016 challenge dataset are used from the training dataset during the fivefold cross-validation to train the proposed system and determine \(\alpha _{\mathrm{optimal}}\). Several evaluation metrics, namely the Dice coefficient, specificity, sensitivity, and accuracy, are measured for performance evaluation of the test images using the proposed ONKM method with \(\alpha _{\mathrm{optimal}} =0.0014\) compared to the k-means, and the \(\gamma \)–k-means methods. The results depicted the dominance of the ONKM method with \(99.29\pm 1.61\%\) average accuracy compared with k-means and \(\gamma \)–k-means methods.     

A 0.1–1.1 GHz inductorless differential LNA with double <Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript>-boosting and positive feedback

A 0.1–1.1 GHz wideband low-noise amplifier (LNA) is proposed in this paper. The LNA is a fully differential common-gate structure. Large equivalent transconductance \((g_m)\) is realized by active \(g_m\)-boost and capacitive cross-coupling. By introducing a positive feedback path, the circuit increases design freedom. It alleviates the tradeoff between input matching, gain and noise performance. The proposed LNA avoids the use of on-chip inductors to save area and cost. A prototype is implemented in standard TSMC 180-nm CMOS technology. From the measurement, the proposed LNA shows a 19 dB voltage gain with a 1 GHz 3-dB bandwidth. The minimum noise figure (NF) is 3.1 dB. The LNA achieves a return loss greater than 10 dB across the entire band and the third-order input-referred intercept (IIP3) is better than \(-\,2.9\) dBm. The core consumes 3.8 mW from 1-V supply occupying an area of 0.03 \(\hbox {mm}^2\).     

A 0.18$$\upmu$$m CMOS voltage multiplier arrangement for RF energy harvesting

This work presents a two-stage voltage multiplier (VM) useful in RF energy harvesting based applications. The proposed circuit is based on the conventional differential drive rectifier, in which the input RF signal has been level shifted using a simple arrangement. This signal is then used to drive the next stage, which has been formed by using gate cross-coupled transistors. As a result, the load driving capability of the proposed architecture increases. The load in this work has been emulated in terms of a parallel RC circuit. The architecture has been implemented using standard 0.18 \(\mu\)m CMOS technology. The measurements of the two-stage conventional VM (CVM) and proposed VM circuits were performed at ISM frequencies 13.56, 433, 915 MHz and 2.4 GHz for R\(_L\) of values 1, 5, 10, 3 and 100 K\(\Omega\) with a fixed value of C\(_L\) equal to 20 pF. The performance evaluation has been done in terms of the power conversion efficiency (PCE) and average output DC voltage. The measured results show an improvement in PCE of 5% (minimum) for 13.56, 433 and 915 MHz frequencies, and up to 2% improvement for a frequency value of 2.4 GHz at the targeted load condition of 5 K\(\Omega ||\)20 pF, when compared with the measured results of the CVM circuit.     

A multi-band low noise amplifier with strong immunity to interferers

A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable \(\pi\) network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (\(IIP_3\)) ranges from ?15 to 0 dBm. Implemented in a 0.13 \(\upmu\)m CMOS technology, the LNA occupies an active area of about 0.29 mm\(^2\). This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A low noise compact class AB buffer amplifier with accurate quiescent current control

The authors present a new low-noise class AB buffer amplifier. The proposed buffer amplifier achieves a low noise with fast settling time and low power consumption. The buffer amplifier circuit attains an input referred noise voltage of 12.8 \( {{\text{nV}} /{\sqrt {\text{Hz}}}} \), a DC gain of 108 dB, a unit-gain frequency of 8 MHz, and rising slew rate of 36 V/μs, as the load capacitance equals 150 pF. The circuit is power efficient when driving large capacitive loads and is well suited for low noise low power analog video buffer applications.