1-V power supply CMOS cascode amplifier

We design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69-dB DC gain, a 2-MHz bandwidth, and compatible input- and output voltage levels at a 1-V power supply. This is done by a novel, current driven bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

1-V power supply high-speed digital circuit technology withmultithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-μm CMOS process     

OTA based on CMOS inverters and application in the design of tunable bandpass filter

A new operational transconductance amplifier (OTA) builds with CMOS inverters only is proposed in this paper. Simulations with typical BSIM3V3 parameters of a 0.35 μm CMOS process have shown a 3.56 GHz gain-bandwidth product under 2.5 V supply voltage. The corresponding total harmonic distortion is equal to 0.46% for 2 V peak–peak differential output voltage. At the same supply voltage, the circuit can provided at each output a voltage swing of 2.25 V peak–peak. From V_DD = 2 V to V_DD = 2.5 V the differential transconductance varies from 72 to 108.4 μΩ⁻¹. The corresponding common mode rejection ratio and the total power consumption are always lower than −31 dBc and 800 μW, respectively. Typical application of a biquad filter is proposed to illustrate the circuit capabilities.     

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter. The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 1.44 GHz, drives an active polyphase filter to generate quadrature LO signals. According to simulations the quadrature phase error shows a typical tuned behavior and stays below 0.8° for the complete tuning range. Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset. The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

A monolithically integrated InGaAs/InP photoreceiver operating witha single 5-V power supply

A monolithic photoreceiver consisting of an InGaAs p-i-n photodiode and a transimpedance preamplifier in which four junction field-effect transistors four level shift diodes, and a feedback resistor are integrated is described. This photoreceiver has been designed to operate with a single 5-V power supply for the purpose of simplifying the whole transmission system. Easily producible device structures were adopted to increase the yield of the photoreceivers. A circuit transimpedance of 965 Ω and a 3-dB frequency of 240 MHz have been obtained for 5-V operation. Transmission of a 400-Mb/s NRZ signal has been achieved     

Four-quadrant analog multiplier based on CMOS inverters

In the article a new implementation of four-quadrant analog multiplier in CMOS technology is proposed. The circuit is based exclusively on CMOS inverters (or similar two-transistor blocks) and operates using quarter square technique. The outstanding feature of the circuit is an extreme suitability for low voltage operation and full compatibility with digital CMOS, since there are only two transistors stacked-up between supply rails. Thus the supplying voltage of this circuit class is the lowest possible one for any particular CMOS technology. The operation principle based on symbolic analysis with simple square model has been fully confirmed by simulations with BSIM3v3 models provided by different silicon foundries and verified experimentally using one of them.     

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

This paper presents possible approaches to the design of a novel low-voltage, low-power, and high-precision current conveyor of the second generation (CCII±) based on the bulk-driven folded cascode operational transconductance amplifier (OTA) with extended input common-mode voltage range. This CCII± utilizes bulk-driven differential pairs to obtain a nearly rail-to-rail input stage at a low supply voltage. The proposed conveyor operates at a low supply voltage of ±400 mV with a reduced power consumption of only 64 μW. A current-mode multifunction filter is presented as an application of the CCII±. This filter provides five transfer functions simultaneously, namely low-pass, band-pass, high-pass, notch, and all-pass. The filter has the following properties and advantages: it employs three bulk-driven current conveyors BD-CCII±, three grounded resistors, and two grounded capacitors, which is suitable for integrated circuit implementation. Furthermore, the input signal is connected to the low-impedance X terminal of the BD-CCII± whereas the output signals are taken from the high-impedance output terminals Z+ and Z−. Finally, the pole frequency and quality factor of the designed filter are tunable independent of each other. PSpice simulation results using the 0.18 μm CMOS technology are included to prove the results.     

A 900-MHz 1-V CMOS frequency synthesizer

A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-μm CMOS technology. The frequency synthesizer consists of a divide-by-128/129 and 64/65 dual-modulus prescaler, phase-frequency detector, charge pump, and voltage-doubler circuit with an external voltage-controlled oscillator (VCO) and passive loop filter. The on-chip voltage-doubler circuit converts the 1-V supply voltage to the higher voltage which supplies the prescaler internally. In this way, the 900-MHz 1-V frequency synthesizer with an external VCO can be achieved. The measured phase noise is -112.7 dBc/Hz at a 100-kHz offset from the carrier, and the synthesizer dissipates 3.56 mW (not including VCOs) from a single 1-V supply when the switching frequency of the on-chip voltage doubler is 200 kHz and the power efficiency of the voltage doubler is 77.8%. The total chip area occupies 0.73 mm²     

一种基于衬底驱动技术的亚1V CMOS混频器

讨论了衬底驱动的工作原理。基于衬底驱动NMOS晶体管,对Gilbert混频器电路结构进行改进设计,实现了超低压混频器。基于TSMC 0.25μm CMOS工艺的BSIM3V3模型,采用Hspice,对混频器进行了仿真。结果显示,该混频器在0.8 V单电源电压下,仍可以对2.4 GHz的正弦信号进行混频,转换增益为-8.5 dB,三阶输入截止点的值为28.4 dB。     

A 1-V operating 256-kb full-CMOS SRAM

A 1-V operating 256-kb full-CMOS SRAM to be used in 1.5-V battery-based applications is presented. A reference word line and address transition detection (ATD) are used as timing control techniques to achieve adjustable timing of critical signals with a 1.5-V battery. The key circuit of the pulse sequence block is the ATD pulse generator circuit. The authors use a newly modified Schmitt trigger delay circuit. To reduce supply line noise in the chip, they needed to lower the peak of bit-line charge-up current. This was done by applying a divided word-line technique and a newly adopted staggered bit-line equalizing pulse technique. The design used a single-polysilicon and double-aluminum process with a full-CMOS memory cell of 8.5 μm×12.8 μm. The chip size is 6.0 mm×9.0 mm     

Op-amps and startup circuits for CMOS bandgap references with near 1-V supply

The design of bandgap-based voltage references in digital CMOS raises several design difficulties, as the supply voltage is lower than the silicon bandgap in electron volts, i.e., 1.2 V. A current-mode architecture is used in order to address the main issues posed by the low supply, but the implementation of the operational amplifier and of dedicated startup circuits deserves some attention. Even if nonstandard devices such as depletion-mode MOS transistors may be helpful to manage the supply scaling, they are seldom available and poorly characterized. Therefore, they must be avoided in a robust design featuring a high portability. This paper proposes some circuit solutions suitable for very low-supply-voltage operation and addresses the main issues of achieving the correct bias point at the power on. A few bandgap references were implemented in digital 0.35- and 0.18-/spl mu/m technologies featuring a nominal output voltage of about 500 mV and minimum supplies from 1.5 to 0.9 V.     

An ultra-high gain low power two stage CMOS op-amp based on inverse aspect ratio self cascode structures

A very high gain (137 dB) two stage CMOS operational amplifier having structural simplicity of classical Widlar architecture has been presented. The differential input stage of proposed operational amplifier has been modified by incorporating inverse aspect ratio self cascode structures biased to operate in subthreshold region, to minimize the classical compensation capacitor to 0.1 pF and results in considerable saving in occupied chip area. P-SPICE simulations in 0.25 μm CMOS technology at ±1 V supply have been carried out to compare the performance of proposed operational amplifier with previously reported designs. The proposed operational amplifier demonstrated better gain-bandwidth product of 1.37 MHz, low power consumption of 21 μW and occupied smaller chip area of <400 (μm)².     

A low power tunable Gm–C filter based on double CMOS inverters in 0.35?μm

In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass G_m?CC Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35???m CMOS technology. Simulation results demonstrate the central frequency tunability from 10?kHz to 2.8?MHz which is suitable for the wireless specifications of Bluetooth (650?kHz), CDMA 2000 (700?kHz) and Wideband CDMA (2.2?MHz) applications. The power consumption of the filter is 445?nW and 178???W at 10?kHz and 2.8?MHz from 3.3?V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215?×?720???m². The proposed approach guarantees the upper bound on THD to be ?40?dB for 300?mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6?dB which is higher than similar works.     

基于CMOS OTA的电流模式KHN滤波器

提出了一种基于ＣＭＯＳ ＯＴＡ的电流模式ＫＨＮ滤波器电路。该电路能同时实现低通、带通及高通滤波器,通过端口相接还可以实现带阻及全通滤波器。整个电路仅含两个接地电容而不含其它无源元件。便于集成。ＰＳＰＩＣＥ模拟表明,该电路有低的灵敏度。     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency G_m-C applications in 130-nm digital CMOS process

This paper presents a 0.25-V supplied bulk-driven symmetrical OTA implemented in 130-nm CMOS process. By operating in weak inversion, and using a distributed layout approach, the OTA can benefit from the voltage reduction and high linearity enabled by halo-implanted transistors. The proposed circuit consumes only 10-nW, features a low transconductance of 22-nS, and a total harmonic distortion of 0.53 % for a 100-mV_pp input voltage, thus making it suitable for low-frequency and low-power \(G_m\) -C applications.     

一种低功耗线性范围宽的跨导放大器及其在滤波器中的应用

本文分析了以往文献中提出的各类跨导放大器(OTA,operational transconductor amplifier)的结构特点,为了能更好地改善线性度并降低功耗,本文提出了一种全差分带电流负反馈的跨导放大器。在1.5V的电源电压下,经cadence仿真平台验证,该跨导放大器的线性范围拓宽到1V,IIP3达到24.80dBm,功耗低于14μW。将此跨导放大器应用到三阶椭圆低通跨导电容(OTA-C)滤波器中,经cadence仿真验证,该滤波器的幅频特性陡峭,IIP3达到13.51dBm,功耗为1.6mW。     

A 1-V 50-MHz Pseudodifferential OTA With Compensation of the Mobility Reduction

This brief presents a high-linearity operational transconductance amplifier (OTA) based on pseudodifferential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the 0.18-mum CMOS process occupies a small area of 4.5 x 10^-3 mm^-2. The measured third-order intermodulation (IM3) distortion with a 400 mV_PP differential input under 1-V power supply voltage remains below -52 dB for frequency up to 50 MHz. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.