A nonvolatile memory circuit-a novel approach

A nonvolatile memory circuit using conventionally available components (transistors and magnetic switching cores) operates on the principle of the two distinct impedance levels of a switching core in the irreversible and reversible regions. It has the property of nondestructive read-out and requires no sensing amplifiers. It is believed that the circuit is useful for systems that require low memory capacity, such as from a few bits to a hundred of bits of information.     

A 180 Kbit Embeddable MRAM Memory Module

A 180 Kbit magnetoresistive random access memory (MRAM) organized as 22 bits by 8 Kwords has been developed for embedding in a 0.28 micron CMOS process. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell with a toggle MTJ. For reads, the memory is architected with word lines connecting a row of bits to bit lines with a pass transistor and two stages of columns selection transistors connecting bit lines to dual sense amplifiers. For writes, a read is first performed to determine the state of bits to be written followed by a toggle decision to enable bit line toggle drivers. Overlapping bit and word line currents toggle the selected bits. The new dual sense amplifier architecture separates the amplifier reference bits from the bias bits thereby improving sensitivity and reducing offset. The write driver uses a switched capacitor and charge sharing to improve ground bounce immunity and reduce area. Embedded test registers control internal memory timing, reference voltages, reference currents and access features enabling detailed characterization of the memory and optimization of the design. An example describing optimization of the write parameters is presented.      

Electrical characteristics of silicon-rare-earth fluoride layered switching structures

Switching and memory effects in the electrical conductance of layered structures based on rare-earth fluorides are investigated. These investigations reveal the existence of high-and low-resistance states in structures of metal-insulator-semiconductor type. It is shown that the characteristics of the low-resistance state of such structures are described by a metal-tunneling insulator-semiconductor model. Fiz. Tekh. Poluprovodn. 32, 1349–1353 (November 1998)     

近场光学存储器

近场光学存储器采用了纳米高新制作技术,具有极高的读出速度和极高的存储密度。本文介绍了近场光学“头”、近场光学记录方法、记录机理和处理方法以及T比特光盘的制造技术和结构。     

Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit

A new multi-valued static random access memory (MVSRAM) cell with a hybrid circuit consisting of a single-electron (SE) and MOSFETs is proposed. The previously reported MVSRAM with an SE-MOSFET hybrid circuit needs two data lines, one bit line for write operations and one sense line for read operations, to improve the speed of the read-out operation, but the proposed cell has only one data line for read/write operations, resulting in a memory area that is much smaller than that of the previous cell, without any reduction of read-out speed.     

Influence of electrical field dependent depletion at metal–polymer junctions on resistive switching of poly(N-vinylcarbazole) (PVK)-based memory devices

Polymer memory devices using Au nanoparticles (Au NPs) incorporated poly(N-vinylcarbazole) (PVK) as the active layer and Al films as the electrodes are investigated. The Al/PVK:Au NPs/Al devices exhibit electrical bistability in the I–V characteristics and show a conductance difference ratio between the high-resistance state (HRS) and low-resistance state (LRS) by a factor of 10⁵. Furthermore, the Au nanoparticle/PVK hybrid memory device can be programmed and exhibits excellent thermal stability up to 154 °C in ambient atmosphere. The current conduction is dominated by Schottky emission at HRS and exhibits Ohmic behavior at LRS. The dependence of the current conduction on temperature reveals the connection between the conduction character and the energy-band offsets at the metal (Al or Au)–PVK junctions. In addition, the resistive switching is correlated with the width of depletion region in PVK, which varies with the change of hole carrier concentration upon applying electrical field.     

Resistive Memory Switching of $hbox{Cu}_{x}hbox{O}$ Films for a Nonvolatile Memory Application

Poly crystalline Cu_xO films produced by plasma oxidation are investigated for nonvolatile memory applications. Reversible bistable resistive switching from a high-resistance state to a low-resistance state, and vice versa, is observed in an integrated Al/Cu_xO/Cu structure under voltage sweeping. More than 3000 repetitive cycles are observed in 180-mum memory devices with an on/off ratio of ten times. Data testing shows that the devices meet the ten-year retention requirement for the storage of programmed logic signals.     

A novel self-aligned highly reliable sidewall split-gate flash memory

A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250/spl deg/C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.     

Direct gravure printing (DGP) method for printing fine-line electrical circuits on ceramics

The tendency toward higher packing densities and higher frequencies for telecommunication devices based on ceramic technology requires smaller dimensions for electrical wiring. Electrical thick-film circuits for ceramic and LTCC-substrates have, up to now, been printed with screen printing, where the printing lines width limit is about 125 /spl mu/m in mass production. A silicone polymer direct gravure printing (Si-DGP) process has been developed to perform smaller dimensions, down to 20 /spl mu/m lines width, for electrical circuitry. In the DGP process, the conductor paste is doctored to the grooves of the gravure and then it is pressed against the substrate. The paste is, thus, printed directly onto the substrate from the patterned gravure. The results showed that, using the DGP process, it was possible to print conductor lines down to 20 /spl mu/m in width. It was also noted that a 100% transfer of paste from the grooves of the gravure could be obtained with commercial pastes using the silicone polymer gravure. A dried thickness of up to 28 /spl mu/m was measured for the narrowest lines. Also conductor lines printed by the Si-DGP method were embedded inside LTCC-module.     

System of nano-silver inkjet printed memory cards and PC card reader and programmer

This work describes the development of inkjet printed, low-cost memory cards, and complementary pair of memory card reader and card reader/programmer for PCs. This constitutes a complete system that can be used for various applications. The memory cards are manufactured by inkjet printing nano-silver ink on photo paper substrate. The printed memory structures have an initial high resistance that can later be programmed to specific values representing data on the cards, the so called Write Once Read Many (WORM) memories. The memory card reader measures the resistance values of the memory cells and reads it back to the computer by USB connection. Using multiple resistance levels that represent different states it is possible to have a larger number of selectable combinations with fewer physical bits compared to binary coding. This somewhat counters one of the limitations of resistive memory technology that basically each cell needs one physical contact. The number of possible states is related to the resolution of the reader and the stability of the WORM memory.     

Influence of the surface roughness of the bottom electrode on the resistive-switching characteristics of Al/Al2O3/Al and Al/Al2O3/W structures fabricated on glass at 300 °C

Resistive-switching devices based on Metal–Insulator–Metal (MIM) structures have shown promising memory performance characteristics while enabling higher density of integration. Usually, these MIM devices are fabricated using different processing conditions including high temperature thermal treatments that could lead to undesirable chemical reactions in the insulator material and at its interface with the metals involved. In this work, we compare the electrical characteristics of MIM devices (fabricated on glass at 300 °C) that use aluminum or tungsten as bottom electrode (BE) in order to study the influence of a highly reactive (aluminum) or inert (tungsten) metal electrode on the memory characteristics. We found that the switching characteristics of Al₂O₃ (from a high-resistance state HRS to a low-resistance state LRS and vice versa), are highly dependent on the surface roughness of the BE, the thickness of Al₂O₃ and the current compliance (CC) which limits the electron density flowing through both top/bottom electrodes.     

An 80-ns 1-Mb flash memory with on-chip erase/erase-verifycontroller

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ². The die area is 32.3 mm². An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor     

Inkjet-printed resistors with a wide resistance range for printed read-only memory applications

Inkjet-printed resistors with resistance values varying over five orders of magnitude were demonstrated on a flexible substrate. The resistivity of printed lines of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) was altered by using different ink formulations and by employing an over-print technique, while the length of the printed resistor line remained unchanged. This technique was then applied to fabricate a printed read-only memory device that consisted of an array of resistors. The concept of printing reliable, visually identical resistors with controlled resistance values provides an important building block for low cost, printed electronic circuit applications.     

The transistor laser

A research team at the University of Illinois at Urbana-Champaign has developed a new, more powerful kind of device, called the transistor laser. The transistor puts out both electrical signals and a laser beam, which can be directly modulated to send optical signals at the rate of 10 billion bits per second. With some further modification, the transistor laser will eventually send a staggering 100 billion bits per second or more. Instead of using relatively slow wires to connect chips stacked together in packages, transistor lasers can be used as optical interconnects, which would let data flow instantaneously to and from memory chips, graphics processors, and microprocessors. There is much work ahead, but unlike the host of self-assembling, blue-sky nanotechnologies currently being touted as the next big thing in optoelectronics, transistor lasers do not need an entirely new fabrication infrastructure for further development or even to go into production.     

A nanoscale nonvolatile memory device made from RbAg4I5 solid electrolyte grown on a Si substrate

A nanoscale nonvolatile memory device made from RbAg₄I₅ solid electrolyte has been made directly on a Si substrate with lateral size scaled down to 100 nm. By applying voltages with different polarity, the device could be switched between high- and low-resistance states. The ratio between the high and low resistances could reach ∼10³, and the low-resistance state showed rectifying diode characteristics. The configured resistances remained nonvolatile after switching, and the device could be switched repeatedly for ∼10³ times. Our results show that the nanoscale nonvolatile memory device can be integrated directly with Si-based circuit and can be potentially used for high-density memory application.     

A 40 ns 64 kbit junction-shorting PROM

The memory is organized as 8192 words/spl times/8 bits. A memory cell consists of a programmable element composed of a p-n junction diode and a vertically connected p-n-p transistor. During programming, the programmable element is changed from the current-blocking state of a reverse diode to the current-conducting state of a shorted junction diode by using the diffused eutectic aluminum process (DEAP). With a selective power switching dual-stage decoder, the power dissipation in the decoder circuit was reduced to 40% of a conventional decoder without power switching. The power saved was used to speed up the multiplexers and the output buffers.     

Anomalous Cells With Low Reset Resistance in Phase-Change-Memory Arrays

Resistance distributions for the reset state in phase-change-memory arrays are studied as a function of the programming conditions. The statistical distribution displays a low-resistance tail, which may potentially affect the resistance window between the two states in the memory device. The majority of tail cells are found to result from the statistical dispersion of the quenching properties of the chalcogenide material and can be corrected by optimizing the programming operation. On the other hand, a residual tail is found, which is characterized in terms of programming, switching, and conducting characteristics. The measured behavior is consistent with extrinsic low-resistance paths in the programmable volume, which shunts the high-resistance amorphous phase and prevents reaching a fully reset resistance. Removal of this extrinsic tail in the reset distribution is demonstrated by careful optimization of the integration process.     

The electrical behavior of nitro oligo(phenylene ethynylene)’s in pure and mixed monolayers

In order to realize molecular electronic devices, molecules with electrically interesting behavior must be identified. One molecule that has potential for use in devices is an oligo(phenylene ethynylene) (OPE) molecule with nitro sidegroup(s). These “nitro” molecules have been reported to show electrical switching with memory behavior, as well as negative differential resistance (NDR). However, different research groups testing the nitro molecules in different test beds have observed different electrical behaviors. In this work, we assembled two different nitro monolayers: one completely composed of nitro molecules and the second a mixed matrix where nitro molecules were separated by dodecanethiol molecules. We used scanning tunneling microscopy to image each of the monolayers and observed that the nitro molecules were effectively inserted into the ordered dodecanethiol monolayer. We tested the electrical behavior of the pure monolayer, as well as the mixed monolayer, in our nanowell test device. The nanowell devices were fabricated on micron-size gold lines patterned on oxide-coated silicon wafers. The gold lines were covered with a silicon dioxide layer, through which a nanometer size well was milled. This nanowell device was filled with a self-assembling monolayer of organic molecules, and capped with titanium and gold. The nanowell electrical results showed switching with memory for the pure nitro monolayer, but not for the mixed monolayer. This switching behavior consisted of a molecule starting in a high conductivity state and switching to a low conductivity state upon application of a threshold voltage. The high conductivity state could only be returned by application of an opposite threshold voltage.     

A 1-GHz logic circuit family with sense amplifiers

This paper describes a newly developed logic circuit family based on dual-rail bit lines and sense amplifiers that is used extensively in a 1.0-GHz, single-issue, 64-bit PowerPC integer processor, gigahertz unit test site (guTS). The family consists of an incrementor, a count-leading-zero, a rotator, and a read-only memory. Each macro consists of a leaf-cell array, dual-rail bit lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read-out scheme sensing the differential voltage of dual-rail bit lines is used. The hardware was fabricated in a 0.25-μm drawn channel length, six-metal-layer (Al) CMOS technology (1.8-V nominal VDD). Wafer testing was performed using a probe card. The macros were tested cycle by cycle by scanning the input data to the read/write address latches and data latches, and scanning the result out from the output receiving latches. Functional testing was performed on guTS macros at frequencies up to 1.0 GHz at 25°C with nominal VDD (1.1 GHz for the ROM)     

Gambling for the mnemonically impaired

We obtain asymptotically tight bounds on the maximum amount of information that a single bit of memory can retain about the entire past. At each of n successive epochs, a single fair bit is generated and a one-bit memory is updated according to a family of memory update rules (possibly probabilistic and time-dependent) depending only on the value of the new input bit and on the current state of the memory. The problem is to estimate the supremum over all possible update rules of the minimum mutual information between the state of the memory at time (n + 1) and each of the previous n input bits. We show that this supremum is asymptotically equal to 1/(2n² ln 2) bit, as conjectured by Venkatesh and Franklin (1991). We use this result to derive asymptotically sharp estimates of related maximin correlations between the memory and the input bits, thus resolving two more questions left open by Venkatesh and Franklin and by Komlos et al. (1993). Finally, we generalize the results to the case of an m-bit memory, again obtaining asymptotically tight bounds in many cases