A Time-Domain Sub-Micro Watt Temperature Sensor With Digital Set-Point Programming

To realize the on-chip temperature monitoring of VLSI circuits, an accurate time-domain low-power CMOS thermostat based on delay lines is proposed. Contrary to the voltage-domain predecessors, the proposed circuit can benefit from the performance enhancement due to the scaling down of fabrication processes. By replacing R-string voltage division and voltage comparator with delay line time division and time comparator, only little static power is consumed. The power consumption and chip size can be reduced substantially. Without any bipolar transistor, the temperature sensor composed of a delay line is utilized to generate the delay time proportional to the measured temperature. Instead of a conventional voltage/current DAC or an external resistor, a succeeding multiplexer (MUX) along with a reference delay line is used to program the set-point. The test chips with mixed-mode design were fabricated in a TSMC CMOS 0.35-mum 2P4M digital process. The chip area is merely 0.4 mm². The effective resolution is around 0.5degC with a 256-to-1 multiplexer and -40degC ~ 80degC nominal temperature range. The achieved measurement error is within plusmn0.8degC for a total of 20 packaged chips over the temperature operation range of commercial ICs. The power consumption is 0.45 muW per conversion and a measurement rate as high as 1 MHz is feasible when necessary.     

Microelectronic capacitance transducer for particle detection

This paper describes the CMOS circuit design of a sensor for detecting changes of capacitance due, for instance, to the incidence of particles or bubbles on the electrodes. The circuit is based on a simple design originating at the University of California, Berkeley, for measuring crosstalk on integrated circuits. The basic front-end sensor circuit comprises eight MOSFETs and has a sensitivity of 40 mV/fF. A differential amplifier receives the outputs from two sensor circuits each having 20-/spl mu/m square inter-digitated electrodes. The resulting sensitivity of the fabricated sensor is 1 V/fF with a noise level equivalent to 10 aF. Monte Carlo circuit simulations have been used to identify transistor dimensions to yield acceptable yield, and prototype custom silicon chips have been fabricated using a 0.8-/spl mu/m CMOS process. Static and dynamic tests, using polyamide particles as small as 10-/spl mu/m diameter, verify correct operation of the sensors. The sensor is now being developed for application in miniature electrical tomography systems.     

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide

2D semiconductor materials are being considered for next generation electronic device application such as thin‐film transistors and complementary metal–oxide–semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS₂ n‐type transistor and a Si nanomembrane p‐type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition‐metal dichalcogenide materials. The fabricated hetero‐CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air‐stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub‐nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics.     

A Novel High-Speed Multiplexing IC Based on Resonant Tunneling Diodes

A new multiplexing IC based on the resonant tunneling diode (RTD) is proposed. The unique negative differential resistance characteristics arising from quantum effects of the RTD enable us to develop a new functional low-power digital circuit. The proposed multiplexing IC consists of two current-mode-logic monostable-bistable transition logic elements (CML-MOBILEs) based on the RTD and a low-power selector circuit block. The proposed circuit has been fabricated by using an InP RTD/ heterojunction bipolar transistor monolithic microwave integrated circuit technology. The multiplexing operation of the fabricated quantum effect IC has been confirmed up to 45 Gb/s for the first time as a monolithic technology based on the quantum effect devices. The dc power consumption is only 23 mW, which is found to be one-fourth of the current state-of-the-art conventional transistor-based multiplexing IC.     

A multinanodot floating-gate MOSFET circuit for spiking neuron models

Spiking neuron models, which represent information in the form of spatiotemporal patterns in spike pulse trains, have attracted much attention recently in the fields of computational neuroscience and artificial neural networks. The information processing abilities of spiking neuron models have been proven superior to those of the conventional analog-type (rate-coding) neural network models. In particular, the spike response model (SRM), which simplifies the biological neuron operation from the viewpoint of spike response, is important for VLSI implementation and various applications. In the SRM, the generation of post-synaptic potentials (PSPs) is essential. The conventional CMOS devices require complicated circuits in order to realize the function of SRM neurons. In this paper, a new device structure using a MOSFET with multinanodot floating-gate arrays is proposed for the synapse component of SRM neurons. This structure can operate at room temperature, as it utilizes thermal-noise-assisted tunneling between nanodots. The structure generates PSPs by taking advantage of the delay in electron movement due to stochastic tunneling processes. The results of single-electron circuit simulation demonstrate the generation of PSPs. The proposed structure has not yet been fabricated. The aim of this paper is to propose guidelines for the development of new nanoscale devices and fabrication technology for intelligent information processing such as that achieved in the human brain.     

Magnetic field enhanced resonant tunneling in a silicon nanowire single-electron-transistor

We report fabrication, measurement and simulation of silicon single-electron-transistors made on silicon-on-insulator wafers. At T-2 K, these devices showed clear Coulomb blockade structures. An external perpendicular magnetic field was found to enhance the resonant tunneling peak and was used to predict the presence of two laterally coupled quantum dots in the narrow constriction between the source-drain electrodes. The proposed model and measured experimental data were consistently explained using numerical simulations.     

Silicon nanowire transistors with a channel width of 4 nm fabricated by atomic force microscope nanolithography

The emergence of an ultrasensitive sensor technology based on silicon nanowires requires both the fabrication of nanoscale diameter wires and the integration with microelectronic processes. Here we demonstrate an atomic force microscopy lithography that enables the reproducible fabrication of complex single-crystalline silicon nanowire field-effect transistors with a high electrical performance. The nanowires have been carved from a silicon-on-insulator wafer by a combination of local oxidation processes with a force microscope and etching steps. We have fabricated and measured the electrical properties of a silicon nanowire transistor with a channel width of 4 nm. The flexibility of the nanofabrication process is illustrated by showing the electrical performance of two nanowire circuits with different geometries. The fabrication method is compatible with standard Si CMOS processing technologies and, therefore, can be used to develop a wide range of architectures and new microelectronic devices.     

Analysis of electromigration effects within various types of aluminum test structures

Advances in integrated circuit fabrication technology over the past two decades have resulted in integrated circuits with smaller device dimensions and larger area and complexity. This evolution of technology highlights electromigration as a major reliability problem in silicon VLSI circuits. Emphasis is placed on the scope and detail of the electromigration test structures themselves, and on the analysis of electromigration effects within various types of aluminum test structures.     

Fabrication and measurement of low-stress membrane mirrors for adaptive optics

We have fabricated low-stress membranes from single-crystal silicon for use as deformable mirrors in adaptive optics. These membranes have lower stress than membranes made from silicon nitride or other materials and therefore are capable of greater deformation than previously used membrane mirrors. Membranes were assembled into devices by flip chip bonding to electrode chips with either 256 or 1024 electrodes. We have characterized devices with static and dynamic tests and compared their performance with an analytical model. We tracked the evolution of strain in the membrane during the device's fabrication and assembly and identified sources of stress and strain in this process. We identified boron dopant concentration as a critical determinant of intrinsic stress in the membrane.     

A two-step methodology for CMOS VLSI reliability improvement: Step one

Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck-at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two-step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre-SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.     

Accurate CMOS-based current conveyors

An integrable circuit technique for implementing both positive and negative second-generation current conveyors (CCII) is described. Since the proposed circuits consist of a differential pair, current sources, and current mirrors, the realization method can result in a fully integrated current conveyor. The realization method is suitable for fabrication in CMOS technology. The performance of the CMOS-based CCIIs is discussed in detail. The basic performances are demonstrated and simulation and experimental results are presented. The DC transfer characteristics for converting resistors are linear over the total dynamic range     

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.     

Fault detection in CMOS circuits by consumption measurement

Some testing problems in CMOS circuits are presented, including stuck-open and stuck-on faults, bridging faults, and excessive leakage in dynamic CMOS circuits. It is shown that the current consumption of a faulty CMOS circuit is several orders of magnitude greater than that of the fault-free circuit: hence, consumption measurement may be a suitable way of testing. Test by consumption measurement provides improved controllability and observability of some faults in comparison with the logic test     

Observation of room temperature negative differential resistance in multi-layer heterostructures of quantum dots and conducting polymers

Multi-layer heterostructure negative differential resistance devices based on poly-[2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylenevinylene] (MEH-PPV) conducting polymer and CdSe quantum dots is reported. The conducting polymer MEH-PPV acts as a barrier while CdSe quantum dots form the well layer. The devices exhibit negative differential resistance (NDR) at low voltages. For these devices, strong negative differential resistance is observed at room temperature. A maximum value of 51 for the peak-to-valley ratio of current is reported. Tunneling of electrons through the discrete quantum confined states in the CdSe quantum dots is believed to be responsible for the multiple peaks observed in the I-V measurement. Depending on the observed NDR signature, operating mechanisms are explored based on resonant tunneling and Coulomb blockade effects.     

New complementary logic circuits using coupled open quantum systems

This paper present new complementary logic circuits that exploit an intrinsic bistability in nanoscale coupled open quantum systems such as wells and wires. When operated with a multiple-phase split-level clocking scheme, the device can latch a binary digit while meeting gain, tolerance, and I/O decoupling requirements at the same time, which was difficult with conventional back-to-back negative differential resistance devices. This same structure in a dual-rail configuration can function as a complete set of classical logic circuits by changing only the connections of the input signals. When these circuits are combined to form a sequential circuit, low power operation is expected, thanks to better voltage scaling, a zero-standby-power equalized state, and efficient charge recycling.     

A complete fabrication route for atomic-scale, donor-based devices in single-crystal germanium

Despite the rapidly growing interest in Ge for ultrascaled classical transistors and innovative quantum devices, the field of Ge nanoelectronics is still in its infancy. One major hurdle has been electron confinement since fast dopant diffusion occurs when traditional Si CMOS fabrication processes are applied to Ge. We demonstrate a complete fabrication route for atomic-scale, donor-based devices in single-crystal Ge using a combination of scanning tunneling microscope lithography and high-quality crystal growth. The cornerstone of this fabrication process is an innovative lithographic procedure based on direct laser patterning of the semiconductor surface, allowing the gap between atomic-scale STM-patterned structures and the outside world to be bridged. Using this fabrication process, we show electron confinement in a 5 nm wide phosphorus-doped nanowire in single-crystal Ge. At cryogenic temperatures, Ohmic behavior is observed and a low planar resistivity of 8.3 kΩ/□ is measured.     

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.     

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25times25 , and the time necessary for convolving a 10²⁴times10²⁴-pixel, 12-bit-accurate image with a 3232-pixel window function of similar accuracy is close to 25 , much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( ~1 mum² and 1mus, respectively), but this option requires a very high (~1%) reproducibility of on currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.     

Split current quantum-dot cellular automata-modeling and simulation

We examine a novel quantum-dot cellular automata device concept using the interaction of resonant tunneling currents through a system of four quantum wells. The interaction of resonant tunneling currents forces the total current to flow predominantly in the wells along one of the two diagonals, effectively polarizing the cell. We refer to this device concept as split current quantum cellular automata (SCQCA). A free cell will settle to a random diagonal, whereas charge interactions between adjacent cells will cause the polarization to synchronize between cells. In contrast with the standard QCA cell, this device does not require tunneling between dots. Electron tunneling occurs along the vertical direction, where highly controllable deposition techniques are able to deposit very thin films and effectively tune the device parameters. Clocking of an SCQCA cell is performed by controlling the bias across the device, and none of the potential barriers between the dots need to be controlled. We believe this device concept lends itself to fabrication using currently available fabrication technologies.