Electro-conductive adhesives for high density package and flip-chip interconnections

Dispensable isotropic conductive adhesives (ICA) and snap-curing anisotropic conductive adhesives (ACA) are developed through the EC funded Brite EuRam project DACTEL #BE95-1503. They show very promising capabilities for high-density applications when compared to benchmark electro-conductive adhesives.As first high-density application, assemblies of ceramic and plastic ball grid array/land grid array (LGA) on FR4 with DAC3-102/14 ICA are realized. Mixed assemblies solder/ICA show poor results, especially during aging. Full polymer LGA assemblies are built successfully. Daisy chains with hundreds of transitions component/substrate present resistances as low as 4 Ω. After comparison with benchmark products, CLGAs show themselves to be particularly reliable under moisture conditioning.Secondly, flip-chip assemblies on board, of medium sized chips bumped with electroless NiAu and using DAC2-143/02 ACA, are performed. Contact resistances as low as 10 mΩ are produced. For this application, reliability results are succinct.Finally, flip-chip assemblies on glass of slim chips with NiAu bump pitch down to 80 μm, by means of the newly developed DAC2-143/02 ACA, are demonstrated. The material shows better performances than a benchmark anisotropic conductive film, where measurements reveal contact resistances lower than the sheet resistance of the transparent indium tin oxide metallization used in display applications. Thermal cycling and temperature storage reveal good behavior of the ACA paste.     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

Material properties of anisotropic conductive films (ACFs) and their flip chip assembly reliability in NAND flash memory applications

In this paper, the material properties of anisotropic conductive films (ACFs) and ACF flip chip assembly reliability for a NAND flash memory application were investigated. Measurements were taken on the curing behaviors, the coefficient of thermal expansion (CTE), the modulus, the glass transition temperature (T_g), and the die adhesion strength of six types of ACF. Furthermore, the bonding processes of the ACFs were optimized. After the ACF flip chip assemblies were fabricated with optimized bonding processes, reliability tests were then carried out. In the pressure cooker test, the ACF with the highest adhesion strength showed the best reliability and the ACF flip chip assembly revealed no delamination at the chip-ACF interface, even after 96 h. In the high temperature storage test and the thermal cycling test, the reliability of the ACF flip chip assembly strongly depends on the T_g value of the ACF. In the thermal cycling test, in particular, which gives ACF flip chip assemblies repetitive shear stress, high value of CTE above T_g accelerates the failure rate of the ACF flip chip assembly. From the reliability test results, ACFs with a high T_g and a low CTE are preferable for enhancing the thermal and thermo-mechanical reliability. In addition, a new double-sided chip package with a thickness of 570 μm was demonstrated for NAND flash memory application. In conclusion, this study verifies the ACF feasibility, and recommends the optimum ACF material properties, for NAND flash memory application.     

Characterization of nonconductive adhesives for flip-chip interconnection

For chip-level interconnection, nonconductive adhesive (NCA) is emerging as one of the promising substitutes for solder interconnection because of its inherent fine-pitch capability and environmental friendliness. The NCA interconnect relies on the mechanical connection between the contacts on the chip and corresponding contacts on the substrate enabled by the compressive stress created as the NCA epoxy cures. The degradation mechanism of NCA technology is, however, relatively less well understood compared to solder interconnects in terms of materials requirements for enhanced reliability performance. This study addresses the impact of material systems employed on the reliability of the packages. This involves characterization of NCA pastes in thermomechanical, hygroscopic swelling, and moisture diffusion properties. The reliability evaluation was carried out using electroless nickel/gold perimeter bumped test chips with daisy-chained connections. Analysis showed that interfacial delamination and open contact were the major failure modes in the NCA package. Pressure cooker test (PCT) performance was improved by using NCA with low-saturated moisture concentration, low coefficient of moisture expansion, and high adhesion. For better performance in the moisture sensitivity test (MST), the key properties required were high shear strength and low moisture diffusivity. Interestingly, filler content shows opposing behavior in the MST versus the PCT. Thus, optimum filler content must be found.     

Research on the contact resistance,reliability, and degradation mechanisms of anisotropically conductive film interconnection for flip-chip-on-flex applications

Although there have been many years of development, the degradation of the electrical performance of anisotropically conductive adhesive or film (ACA or ACF) interconnection for flip-chip assembly is still a critical drawback despite wide application. In-depth study about the reliability and degradation mechanism of ACF interconnection is necessary. In this paper, the initial contact resistance, electrical performance after reliability tests, and degradation mechanisms of ACF interconnection for flip-chip-on-flex (FCOF) assembly were studied using very-low-height Ni and Au-coated Ni-bumped chips. The combination of ACF and very-low-height bumped chips was considered because it has potential for very low cost and ultrafine pitch interconnection. Contact resistance changes were monitored during reliability tests, such as high humidity and temperature and thermal cycling. The high, initial contact resistance resulted from a thin oxide layer on the surface of the bumps. The reliability results showed that the degradation of electrical performance was mainly related to the oxide formation on the surface of deformed particles with non-noble metal coating, the severe metal oxidation on the conductive surface of bumps, and coefficient of thermal expansion (CTE) mismatch between the ACF adhesive and the contact conductive-surface metallization. Some methods for reducing initial contact resistance and improving ACF interconnection reliability were suggested. The suggestions include the removal of the oxide layer and an increase of the Au-coating film to improve conductive-surface quality, appropriate choice of conductive particle, and further development of better polymeric adhesives with low CTE and high electrical performance.     

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.     

Effects of Heating Rate on Material Properties of Anisotropic Conductive Film (ACF) and Thermal Cycling Reliability of ACF Flip Chip Assembly

In this paper, the effects of heating rate during anisotropic conductive film (ACF) curing processes on ACF material properties such as thermomechanical and rheological properties were investigated. It was found that as the heating rate increased, the coefficient of thermal expansion (CTE) of the ACF increased, and the storage modulus and glass transition temperature $(T _{g})$ of the ACF decreased. Variation of the ACF material properties are attributed to cross-linking density, which is thought to be related with the ACF density. In addition, as the heating rate increased, the minimum viscosity of the ACF decreased and the curing onset temperature increased during the curing process. The similar phenomenon was also found in in-situ contact resistance measurement. As the heating rate increased, contact resistance establishing temperature increased and the contact resistances of the ACF flip chip assemblies decreased. The decrease in contact resistance was due to larger conductive particle deformation which leads to larger electrical contact area. The effect of the heating rate of ACFs on thermal cycling (T/C) reliability of flip chip assemblies was also investigated. As the heating rate increased, the contact resistances of the ACF flip chip assembly rapidly increased during the T/C test. The T/C reliability test result was analyzed by two terms of shear strain and conductive particle deformation. Reduced gap of joints due to reduced ACF viscosity resulted in larger shear strain. Moreover, many cracks were observed at metal-coated layers of conductive particles due to larger deformation.      

Effects of the Functional Groups of Nonconductive Films (NCFs) on Material Properties and Reliability of NCF Flip-Chip-On-Organic Boards

Nonconductive films (NCFs) are one of the polymer interconnect materials for flip-chip interconnection. NCFs containing no conductive particles play several roles such as adhesion, insulation, and underfilling at the same time. The most important issue of NCF flip-chip-on-board (FCOB) assemblies is thermal cycling reliability. Thermomechanical properties of cured NCFs, such as glass transition temperature (T_g), storage modulus (E'), and coefficient of thermal expansion (CTE), significantly affect the thermal cycling reliability of NCF FCOB assemblies. In this paper, the improvement of thermomechanical properties of NCFs was investigated by controlling the number of functional groups of NCF resins. To compare the reliability of conventional and modified NCF FCOB assemblies after thermal cycling test, electrical analysis and scanning acoustic microscopy investigation were performed. Thermal deformations of NCF FCOB assemblies under thermal cycling environment were also investigated, and quantitatively compared using high sensitivity Twyman-Green interferometry and portable engineering Moire interferometry. According to these results, the functional groups of NCFs have significant effects on thermomechanical properties of cured NCFs, thermal deformation, and thermal cycling reliability of NCF-bonded FCOB assemblies. As a result, the functionality modified NCF FCOB assemblies showed significantly enhanced reliability compared conventional NCFs in thermal cycling test.     

Reliability of adhesive joined thinned chips on flexible substrates under humid conditions

Thin chips are an interesting option for reducing the thickness of an electronics package. In addition to the reduced size, thinned chips are flexible and can dissipate more heat than thicker ones. Joining of the thin chips can be done using several different techniques. Of these, anisotropic conductive adhesives (ACA) are an interesting option as they have several advantages, such as low bonding temperature and capability for high density interconnections. The reliability of ACA flip chip joints under thermal cycling conditions has been found to increase when thinned chips are used. However, the effect of humidity has not been fully explored. In this study the reliability of thinned chips (50 μm) under humid conditions was investigated using thin flexible substrates. Seven test lots were assembled with thinned chips using two different ACA films and liquid crystal polymer (LCP), polyimide (PI) and thin FR-4 substrates. A high humidity and high temperature test was used to study the reliability of the interconnections. A finite element model (FEM) was used to analyse the stresses in the test samples during testing. Several failures occurred during the test and significant differences between the substrates were seen. Additionally, bonding pressure was found to be a critical factor for the reliability under the humid conditions.     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Packaging of integrated solid-state power assembly cells: athermomechanics-based approach

The design of integrated solid-state power assemblies presents unique challenges originating from the high current, voltage, and temperature levels at which they operate. Specifically, they are subject to high levels of internal mechanical stress owing to the dissimilar materials from which they are fabricated coupled with the higher temperatures and currents that develop within the modules during their operation. However, as future demands grow for compact power assemblies with ever-increasing controlled-power density coupled with low cost and straightforward manufacturability, the necessity for a predictive capability for their reliability is greater than ever. Surprisingly, despite the lack of a widely accepted methodology for such designs, much of the basic knowledge is in place. Therefore, the goal of this article is to summarize the main modes of failure in power assemblies, the corresponding material degradation mechanisms and driving forces, and the material properties that are required to help stimulate further developments in this area. A vital component of the approach presented here is to base the understanding on a rigorous knowledge of the physics involved in failure     

Die stress characterization in flip chip on laminate assemblies

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.     

Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies

Flip-chip technology is increasingly prevalent in electronics assembly [three-dimensional (3D) system-in-package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The obtained constitutive law of the HEM was then implemented in finite-element software (Abaqus^®). Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization–localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely the stress and strain fields in these phases, two models of structural zoom, taking into account the real solder bump geometry, have been tested. The obtained local stress and strain fields corroborate the experimentally observed damage initiation of the solder bumps.     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology     

Comparative studies on solder joint reliability of CTBGA assemblies with various adhesives using the array-based package shear test

This paper discusses the influences of various adhesives on board-level shear strength of ChipArray® Thin Core Ball Grid Array (CTBGA) assemblies through an innovative reliability evaluation approach, i.e. array-based package (ABP) shear test. It is found that the adhesives do enhance the shear strength for all the test categories as compared with the assemblies without adhesives (w/o A), but the degree of improvements between different strategies vary quiet a lot. The specific shear strength is affected by a number of factors, in which dispending patterns and material properties of the adhesives used influences it obviously. In general, the adhesives with high storage modulus and large dispensing volume are preferred, for example, stiff full or partial capillary flow underfills. In order to further understand the failure mechanism of the CTBGA during the ABP shear test, failure analysis on tested devices are also conducted using side view optical microscopy, scanning electron microscope (SEM) and energy dispersive X-ray (EDX), the results indicate that the predominant failure mode changes from PCB pad lift/cratering to fracture at package side intermetallic compound (IMC)/solder interface with increasing dispensing volume and storage modulus, which basically improves the solder joint reliability of CTBGA assemblies.     

Novel Ceramic Composite Substrates for High-Density and High Reliability Packaging

This paper presents the development and evaluation of a large-area carbon-silicon carbide (C-SiC) based composite board material that has the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (> 200 GPa) and Si-matched coefficient of thermal expansion (CTE) (~ 2.5 ppm/degC) of ceramics. Test vehicles were fabricated using C-SiC boards for assessing ultra-fine pitch solder joint reliability without underfill as well as the reliability of high-density wiring with microvias on the board. Finite element reliability models were developed to simulate the thermomechanical behavior of test vehicles. From the finite-element simulations as well as accelerated reliability tests, the high stiffness low-CTE C-SiC boards did not show any premature solder joint fatigue failure or dielectric cracking. Furthermore, the C-SiC boards show minimal via-pad misalignment and support the multilayer buildup structure required to achieve very high wiring density. The modeling and experimental results suggest that the low-cost large-area ceramic matrix composite (C-SiC) has superior thermomechanical properties, and is, therefore, a promising candidate substrate material for the emerging microelectronic systems.     

Field reworkable underfill materials for flip chip on boardassemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies     

Optimization of Epoxy-Barium Titanate Nanocomposites for High Performance Embedded Capacitor Components

One of the most promising avenues to meet the requirements of higher performance, lower cost, and smaller size in electronic systems is the embedded capacitor technology. Polymer-ceramic nanocomposites can combine the low cost, low temperature processability of polymers with the desirable electrical and dielectric properties of ceramic fillers, and have been identified as the major dielectric materials for embedded capacitors. However, the demanding requirements of mechanical properties and reliability of embedded capacitor components restrict the maximum applicable filler loading (<50vol%) of nanocomposites and thereby limit their highest dielectric constants (<50) for real applications. In this paper, we present a study on the optimization of the epoxy-barium titanate nanocomposites in order to obtain high performance, reliable embedded capacitor components. To improve the reliability of polymer-ceramic nanocomposites at a high filler loading, the epoxy matrix was modified with a secondary rubberized epoxy, which formed isolated flexible domains (island) in the continuous primary epoxy phase (sea). The effects of sea-island structure on the thermal mechanical properties, adhesion, and thermal stress reliability of embedded capacitors were systematically evaluated. The optimized, rubberized nanocomposite formulations had a high dielectric constant above 50 and successfully passed the stringent thermal stress reliability test. A high breakdown voltage of 89MV/m and a low leakage current of about 1.9times10^-11A/cm² were measured in the large area thin film capacitors     

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.