Fast, quasi-3D modeling of base resistance for circuit simulation

Modifications are made to a finite-difference device simulator (PISCES) to model distributed base resistance. The simulator is modified to run in a quasi-3-D mode in which two numerically simulated dimensions model the lateral flow of the base current, and the third dimension is modeled with the modified Gummel-Poon (MGP) equations. The modulation of the intrinsic base sheet resistivity and the base current injection at each node are determined by the MGP model. Basewidth modulation, high injection, emitter debiasing, bias dependence of current paths, and interactions among these effects are studied for a variety of drawn geometries, sheet resistances, and temperatures. It is found that the standard models used in circuit simulation (SPICE) do not adequately model some of these effects. A model that adds an extra term into the function of base resistance is introduced to model these effects. Performing curve fits to the simulation results allows the base resistance parameters to be expressed as a polynomial sum in terms of geometry, the intrinsic and extrinsic sheet resistivities, and temperature     

钟控神经元MOS晶体管的改进HSPICE宏模型

为了解决传统钟控神经元MOSSPICE模型无法进行连续若干个周期瞬态分析的问题,提出了一种改进的钟控神经元MOSSPICE子电路宏模型,采用HSPICE对器件进行了建模,并对模型进行了验证。验证结果表明,改进的模型既适用于普通神经元MOS,可以进行直流特性扫描分析,也可以进行瞬态特性分析;由于模型具有自动"记忆"预充电阶段输入端电平的功能,因此即使在不同的周期输入端所接固定电平不同,也可以进行连续任意个周期的瞬态特性仿真,从而使改进的模型具有更大的灵活性和实用性。     

A modified model of the light amplifying optical switch (LAOS)

A new analytical circuit model of the light amplifying optical switch (LAOS) is proposed. The static I-V curve, the switching voltage, and the input-output characteristics can be calculated from this model. The model is based on deriving an expression for the nonlinear current gain of the heterojunction phototransistor (HPT). The switching mechanism and the I-V characteristics of the LAGS is studied in the context of optical and/or electrical feedback. The nonlinear current gain of the HPT, and the Early effect are the main factors which are responsible for the thyristor-like characteristics of the LAOS. An external feedback resistor is also added to achieve the appropriate switching condition and build up the feedback mechanism. A bistable system using a LAGS is also studied as well as the device hysteresis width     

MOSFET substrate current model for circuit simulation

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120°C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented     

A new drain current model for short-channel MOSFETs

Reduction of channel length makes the channel current to be less than that of drain current. In this paper, by using multiplication factor model [Proc. IEEE IRPS. (1996) 318, Proc. IEEE IRPS (1999) 167] and a simple approximation of the collector current of PBT the drain current in short-channel MOSFETs is modeled and simulated. This model makes use of four parameters, which by extracting them for each device, it is possible to calculate total drain current. The simulation results from this model are compared with the results obtained from MINIMOS, in which match observed between them.     

A unified small-signal simulation algorithm for SMPS

The small-signal behavior of a frequency controlled resonant converter is modeled as an equivalent pulsewidth modulation (PWM) converter. By this model, a recently developed simulation algorithm for PWM converter is modified to simulate both the open-loop and closed-loop small-signal behavior. Experimental results show that this approach is accurate and efficient.     

Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance–inductance–capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.      

A new physical model of the light amplifying optical switch (LAGS)

A new physical model of determining the static I-V curve of the light amplifying optical switch (LAOS) is derived. The model is based on deriving the currents of the HPT and the feedback current of the LAOS. The feedback currents for optical and/or electrical feedback are determined by solving the continuity equation in the collector and the base of the HPT. A negative resistance region in the I-V curve is obtained and controlled by varying the feedback coefficient of the device and the Early effect coefficient. The main factors affecting the negative resistance region are the feedback coefficient, Early effect, the recombination currents in the emitter-base space-charge region, and the ratio of the collector to base doping. The switching voltage of the device is also calculated for different parameters     

Large-signal performance of microwave transit-time devices in mixed tunneling and avalanche breakdown

A large-signal model for Read-type diode structures with narrow generation-region widths where mixed tunneling and avalanche exist is given. The generation region is modeled by use of a modified Read equation along with effective ionization rates. The injected current pulse, which is formed in the generation region, is calculated in isolation from the drift region in order that the effects of tunneling current can be clearly shown. The drift region is modeled by use of difference-equation versions of the device equations and is suitably interfaced to the generation region. The large-signal model of the total device is used to calculate the device admittance and efficiency. Large-signal results for GaAs and Si devices are given and the results are discussed and compared.     

Numerical analysis of capacitance compact models for organic thin-film transistors

Analytical expressions for the gate-voltage dependence of the channel capacitance and the gate-to-contacts overlap capacitances in top-contact organic thin-film transistors (OTFTs) are derived and implemented in an organic compact capacitance model. The resulting modified model is verified by experimental data of transistors with constant mobility. The same model is analyzed by numerical simulations for OTFTs with a voltage-dependent mobility. The simulation results indicate that the quasistatic model describes well the simulated capacitances. In accumulation, the modeled values are slightly overestimated because of the generally accepted assumption of the charge-sheet model. It is also demonstrated that the quasistatic regime occurs at lower frequencies because of the reduced mobility at lower charge carrier concentrations.     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

一种改进的4H-SiC MESFET大信号解析模型

提出了一种基于器件物理和结构参数并可直接应用于射频电路CAD工具的4H-SiC MESFET大信号解析模型.大信号模型基于4H-SiC MESFET的物理工作机理,源漏电流模型采用Materka的改进模型,沟道长度调制系数和饱和电压系数采用了栅源电压的一次函数建模;大信号电容模型采用电荷-电压(Q-V)的电容积分形式.该大信号模型已经应用在CAD工具中.模拟结果与实验结果符合良好,模型的有效性得到验证.     

An accurate CAD model for the ambipolar a-Si: H TFT

The ambipolar output drain current versus drain voltage characteristics of hydrogenated amorphous silicon thin-film transistors are modeled by a method intended for use in computer-aided design programs. An accurate model has been developed that uses a modified experimental sheet conductivity curve to predict the output drain characteristics over many orders of magnitude of the drain current in both the n-channel and p-channel modes of operation. Analytical expressions for the drain current are developed.     

Numerical simulation of stress evolution during electromigration in IC interconnect lines

A finite element simulation of stress evolution in thin metal film during electromigration is reported in this paper. The electromigration process is modeled by a coupled diffusion- mechanical partial differential equations (PDEs). The PDEs are implemented with a plane strain formulation and numerically solved with the finite element (FE) method. The evolutions of hydrostatic stress, each component of the deviatoric stress tensor, and Von Mises' stress were simulated for several cases with different line lengths and current densities. Two types of displacement boundary conditions are considered. The simulation results are compared with Korhonen's analytical model and Black and Blech's experimentalesults.     

A generalized MoM-SPICE iterative technique for field coupling to multiconductor transmission lines in presence of complex structures

A generalized method of moments (MoM)-SPICE iterative technique for field coupling analysis of multiconductor transmission lines (MTLs) in the vicinity of complex structures is presented. Telegrapher's coupling equations are modified with additional distributed voltage and current sources for more accurate analysis of the total current induced onto transmission line bundles in the presence of complex structures. These additional voltage and current sources are introduced to enforce the electric field boundary condition and continuity equation on MTLs beyond the quasi-static regime. The surrounding structure is modeled via the MoM and a SPICE-like simulator is used to simulate equivalent circuit model of the MTLs extracted via the partial element equivalent circuit method. The proposed technique is based on perturbation theory with the quasi-static current distributions on the transmission lines still assumed to be dominant. Validation examples for single and MTLs are given in the presence of complex structures.     

Analytical modeling of oxide breakup effect on base current in n+-polysilicon emitter bipolar devices

The authors have modeled the base current change with different percentages of broken interface-oxide area (interface void). A pseudo-two-dimensional structure of dual channels of minority-carrier transport at the interface between the polysilicon and the silicon emitter, is constructed in analogy with an electrically equivalent conductance network. Using the conductance network, an analytical expression of base current is easily derived. For typical polysilicon emitter devices of ~10-15 Å interface oxide, the experimental results show that the strong dependence of base current on the fraction of interface void can be modeled. The simulation predicts that the base current will be insensitive to the fraction of interface oxide breakup for very thin interface-oxide polysilicon emitter devices. Recent reports on finding a process window between current gain and emitter resistance optimization in a certain range of interface breakup ratios are confirmed by the model     

High-speed InP-InGaAs heterojunction phototransistors employing anonalloyed electrode metal as a reflector

High-speed InP-InGaAs heterojunction phototransistors (HPT's) with a base terminal (three-terminal HPT's) have been fabricated. These HPT's have nonalloyed electrodes functioning as reflectors and a configuration in which light is incident through the substrate. These features lead to an increase in quantum efficiency in spite of the thin base and collector light-absorbing layers. Optical gain dependence on collector current is weak because of the low recombination current at the emitter-base interface. Maximum optical-gain cutoff frequencies of 22 and 14 GHz are obtained for a 3×3-μm² emitter HPT illuminated by 1.3- and 1.55-μm light, respectively. This HPT has the capability of operating as a high-speed heterojunction bipolar transistor (HBT) as well. A current-gain cutoff frequency (f_T) of 128 GHz is obtained for a 3×9-μm² emitter HBT fabricated on the same wafer. Equivalent circuit analysis, in which all the components are determined by measuring both the electrical and optical characteristics of a three-terminal HPT, shows good agreement with experimental results     

Charge-control modeling of power bipolar junction transistors

This paper describes an improved lumped circuit model of power bipolar junction transistors (BJTs) that can predict the turn-off fall time to a greater accuracy than currently available models. Though the existing models simulate the storage time and delay time to a good accuracy, the fall time performance is neglected. This is because the existing models do not account for the charge decay due to recombination. The model presented in this paper is based on the charge dynamics of the device. The charge dynamics are explained in detail using simulation results from an advanced two-dimensional (2-D) device and circuit simulator. Based on a physical understanding of the charge dynamics, this model is implemented to incorporate the charge decay due to recombination to account for the current tail during turn-off. The lumped-circuit model is implemented in PSPICE using the existing quasisaturation model along with controlled sources. To validate the model, the device was subjected to hard- as well as soft-switching renditions (zero current switching and zero voltage switching). The modeled results are observed to have a good match with measured results     

Estimation of sideslip angle and cornering stiffness of an articulated vehicle using a constrained lateral dynamics model

In this paper, a constrained lateral dynamics model of articulated vehicles and an algorithm for estimating sideslip angle and cornering stiffness are proposed. The articulated vehicle was modeled using the bicycle model, linear tire model, and modified Dug-off model. The normal force of each axle included in the model was estimated based on the longitudinal load transfer model. Physical constraints were applied to reduce model states. Accurate sideslip angle and cornering stiffness are essential for vehicle control safety and autonomous driving performance. The sideslip angle and cornering stiffness were simultaneously estimated using a dual linear time-varying (LTV) Kalman filter. The observability matrix guaranteed the convergence of the proposed estimation algorithm. The estimation performance was verified by simulation with TruckSim and an experiment using an articulated bus.     

A CMOS mismatch model and scaling effects

In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations. In addition, a √n-law model is developed for modeling gate-finger dependence of mismatch