Low-power compact tunable quenching configuration for minimizing afterpulsing in single-photon avalanche diodes

This paper unveils two efficient free running (FR) quenching circuits with the aim of reducing quenching time (QT) to minimize avalanche charge. Likewise, one circuit is compactly designed with low power consumption, suitable for single-photon avalanche diode ( SPAD) with hold-off time below 10 ns. In second circuit, tunable hold-off and reset-time are provided within a wide range without decreasing QT, which are desirable in many applications. Proper operation and circuit uncertainty is assessed by Monte Carlo analysis in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology. In a bid to do a comparison between previously reported circuits and the proposed circuits, they are simulated with same SPAD model and parameters and results corroborate the proposed circuits guarantee active quenching time (AQT) of below 1 ns. Proposed circuits with current and area consumption of 0.74 μA, 32 μm² for 7-ns dead time and 16.2 μA, 93 μm² for 21-ns dead time are more efficient in terms of QT, area, and power consumption in comparison with other works.     

A Single Photon Avalanche Diode Implemented in 130-nm CMOS Technology

We report on the first implementation of a single photon avalanche diode (SPAD) in 130 nm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD is fabricated as p+/n-well junction with octagonal shape. A guard ring of p-well around the p+ anode is used to prevent premature discharge. To investigate the dynamics of the new device, both active and passive quenching methods have been used. Single photon detection is achieved by sensing the avalanche using a fast comparator. The SPAD exhibits a maximum photon detection probability of 41% and a typical dark count rate of 100 kHz at room temperature. Thanks to its timing resolution of 144 ps full-width at half-maximum (FWHM), the SPAD has several uses in disparate disciplines, including medical imaging, 3D vision, biophotonics, low-light illumination imaging, etc.     

Single Photon Counting Module Based on Large Area APD and Novel Logic Circuit for Quench and Reset Pulse Generation

We present the design, implementation, and characterization of a single-photon counting module (SPCM) based on large-area avalanche photodiode (APD) and new logic circuit based on TTL integrated circuits (ICs) for generating precise quench and reset delays. Low dark count rate, high linearity of 2 MHz, maximum dynamic range of 12 MHz, and minimum dead time of 35 ns have been achieved with 0.2 mm peltier-cooled single photon avalanche diode (SPAD) [model C30902S-DTC, Perkin Elmer Optoelectronics (PKI)]. The developed module was fiberized and tested for the detection of fluorescently labeled DNA sequences. Detection sensitivity at the level of single fluorescent molecule has been demonstrated.     

Photon-timing detector module for single-molecule spectroscopy with 60-ps resolution

Advanced fluorescence measurements on single molecules demand single-photon detectors with high-quantum detection efficiency, low noise, and high time resolution. We have developed a compact (82/spl times/60/spl times/30 mm) and versatile single-photon timing module (SPTM), based on a planar epitaxial single photon avalanche diodes (SPAD) working with a monolithic integrated active quenching and active reset circuit (i-AQC) and cooled by a Peltier element. The main operating parameters are computer controlled via RS-232 interface and the photon counting rate can be continuously monitored. The photon detection efficiency is 45% at 500 nm with cooling at -15/spl deg/C, the dark counting rate is 5 c/s with SPAD operating at 5 V excess bias voltage, 10c/s operating at 10 V. The time resolution obtained with tightly focused illumination has 60-ps full-width at half-maximum. Comparative tests with the SPTM prototype and with an advanced commercially available photon counting module confirmed that the time resolution and sensitivity of the SPTM make it possible to resolve and measure even short lifetime components of a single molecule. The SPTM thus made possible experiments leading to a deeper insight into angstrom-scale structural changes of single-protein molecules.     

A CMOS voltage regulator for passive RFID tag ICs

A low‐power voltage regulator for passive RFID tag ICs is proposed in this paper. It consists of a self‐biased mutually compensated voltage reference, a low dropout (LDO) voltage regulation circuit and a power‐on‐reset (POR) circuit. It is fabricated in a commercial 0.18?µm CMOS technology and applied to a passive UHF RFID tag IC. The total quiescent current is 700 nA under a 1.8‐V supply. The output voltage of the regulator is 1.45 V with load capability of 50 µA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/^°C, respectively. A POR signal with width pulse of 150 ns is generated for the digital part in the tag IC. Copyright © 2010 John Wiley & Sons, Ltd.     

Design and Simulation of Solid State Pulser with Fast Rise Time and Double-exponential Waveform

Voltage pulses with fast rise time can be obtained from Marx circuits based on avalanche transistors. In this research, the ZETEX avalanche transistors are used as the switches in a Marx circuit to generate stable voltage pulses with double-exponential waveform and fast rise time. By using these transistors, the circuit is able to generate higher pulsed voltage with fewer stages. A three stages and a ten stages Marx circuit, as well as their triggering circuits, are designed. The two Marx circuits are also tested by simulations based on the Pspice code and by experiments, results of which are consistent with each other. With the ten stages Marx circuit, we obtain positive and negative pulses with the rise time of about 1.5 ns, the amplitude above 1 100 V, and the pulse width below 5 ns. It is proved that the proposed Marx circuit equipped with avalanche transistors could be an effective kind of solid-state pulse generator.     

Improved active‐diode circuit used in voltage doubler

An improved active‐diode circuit, which makes use of positive feedback to achieve fast on/off transition, is presented in this paper. The proposed active‐diode circuit can be embedded into a voltage doubler to replace the commonly used dead‐time circuit and to eliminate reverse current. In addition, the relationship between oscillation frequency, boosting and output capacitances, load‐ and on‐resistances of the power switch and the output voltage is analysed, to investigate a methodology to retain high voltage gain of a voltage doubler. The proposed active‐diode circuit is applied to a voltage doubler implemented in a commercial 0.35‐µm process with threshold voltage of about 0.68 V. The input voltage, maximum output current and oscillation frequency of the voltage doubler are 1 V, 1 mA and 0.4 MHz, respectively. Moreover, the used boosting and output capacitances are 22 nF. The highest power efficiency achieved is 83% at a load current of 0.47 mA. Copyright © 2010 John Wiley & Sons, Ltd.     

一种纳秒级脉冲源的仿真及研制

对一种以射频三极管为主要元件的脉冲产生电路进行了计算和试验研究,研制了用于模拟PD信号试验的放电源,设计了储能电容为10pF和20pF的两种脉冲电路,讨论了放电源中主要器件雪崩三极管的雪崩效应理论,推导出三极管雪崩过程的简化模型,用电路仿真软件Pspice仿真分析该电路中储能电容和电源电压对脉冲波形的影响。详细讨论了实际制作过程中的注意事项和元器件的选择方法。实测储能电容为10pF和20pF的PD源脉宽分别为980ps和1180ps,幅值分别为8.9V和11.6V。结果表明,理论和仿真分析的结论一致。     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

一种超宽带窄脉冲信号发生器的设计

宽度窄、幅度大的脉冲生成是探地雷达系统中要解决的关键问题之一.本文在比较了几种不同实现电路的优缺点,详细分析了雪崩三极管原理的基础,提出利用雪崩三极管的雪崩特性,实现超宽带、窄脉冲的生成.文中给出了电路原理图和实验结果,电路分为正、负脉冲2部分,可生成底宽为纳/亚纳秒级、正、负脉冲的峰-峰值高达160 V的窄脉冲信号,并且脉冲拖尾的振荡起伏小,很好地满足了雷达系统的宽度窄、幅度大的要求.电路结构简单、参数可调、移植性强、适用范围广.     

基于雪崩三极管的高重频高压纳秒脉冲产生方法综述

激发大气压脉冲等离子体通常对施加脉冲的要求是k V级幅值、ns级前沿和宽度、k Hz级重复频率,尤其要求脉冲前沿和宽度尽量小,雪崩三极管脉冲产生电路非常适合于这样的要求。本文综述了基于雪崩三极管的脉冲产生方法。首先介绍了雪崩三极管的基本原理和研究概况,进而介绍了多管串联电路、多级Marx电路、多管并联电路以及脉冲截断电路四种典型电路结构的研究现状,分析了各电路的性能特点,并以多级Marx电路为例理论分析了影响输出脉冲幅值、前沿、后沿、脉宽、重复频率、效率和稳定性等参数的关键因素。最后介绍了多管串联Marx电路、多管并联Marx电路以及多路Marx并联电路三种组合型脉冲产生电路的研究进展,并对基本原理进行了分析。     

CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A CCII‐based non‐inverting Schmitt trigger and its application as astable multivibrator for capacitive sensor interfacing

This paper presents a novel second‐generation current conveyor (CCII)‐based non‐inverting Schmitt trigger topology. By means of the use of only three resistances, it is possible to set easily the threshold values or, in addition, the trigger can be set also to work as a zero‐voltage comparator. The theoretical working principle has been confirmed through PSpice simulations implementing an integrated CCII, designed in a low‐cost standard complementary metal–oxide–semiconductor technology (Austria Micro Systems (AMS) 0.35 µm) with low‐voltage low‐power characteristics, and then by experimental tests on the fabricated printed circuit board prototype through the use of the commercial component AD844 (Analog Devices) as CCII. As its main application example, the presented trigger has been employed to implement an astable multivibrator proposed here as a capacitive sensor interface capable to accurately detect about five decades of capacitive variations in the range of [100 pF–5.5 μF] with a maximum relative error lower than ±10%. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel active auxiliary circuit for efficiency enhancement integrated with synchronous buck converter

In this paper, a novel auxiliary circuit is introduced for the synchronous buck converter. This auxiliary circuit provides zero‐current, zero‐voltage switching conditions for the main and synchronous switches while providing zero‐current condition for the auxiliary switch and diodes. The proposed active auxiliary circuit integrated with synchronous buck converter that emanates to zero‐voltage transition (ZVT)–zero‐current transition (ZCT) pulse width‐modulated (PWM) synchronous buck converter is analyzed, and its operating modes are presented. The additional voltage and current stresses on main, synchronous and auxiliary switches get decimated because of the resonance of the auxiliary circuit that acts for a small segment of time in the proposed converter. The important design feature of soft‐switching converters is the placement of resonant components that mollifies the switching and conduction losses. With the advent of ZVT–ZCT switching, there is an increase in the switching frequency that declines the resonant component values in the converters and also constricts the switching losses. The characteristics of the proposed converter are verified with the simulation in the Power Sim (PSIM) software co‐simulated with MATLAB/SIMULINK environment and implemented experimentally. Copyright © 2016 John Wiley & Sons, Ltd.     

基于模块化Marx电路和传输线变压器的重频纳秒脉冲源设计

重频纳秒脉冲激励的大气压等离子体放电具有反应活性高等优点。设计了基于模块化雪崩三极管Marx电路和传输线变压器的重频纳秒脉冲源。计算不同Marx模块的导通时延和输出波形的抖动,研究了磁心数量、位置和形状对于输出波形的影响。磁心电感越大、外径与内径之比越大,且位于传输线变压器第一级和最高一级时对脉冲叠加效率的提升作用越明显。提出直接叠加和传输线变压器两种脉冲叠加方式组合的方法,进一步提高输出电压。整体脉冲源可以在50~300Ω负载产生2~14k V,高阻负载产生4~25k V,前沿3.8ns,脉宽7~15ns,重复频率0~10k Hz的重频纳秒脉冲电压,装置结构紧凑,参数调节灵活,方便携带。     

适用于探地雷达应用的低过冲平衡脉冲发生器

设计了一种新型的超宽带ns级低过冲平衡脉冲发生器.该脉冲发生器包含驱动电路、雪崩三极管脉冲电路和脉冲整形电路3部分,驱动电路用以锐化触发脉冲;雪崩三极管脉冲电路采用独特的晶体管级联结构产生大幅度的高斯脉冲;脉冲整形电路利用并联端接电阻网络和肖特基二极管减小信号反射,最后使用巴仑产生平衡的高斯脉冲,该电路最高可以在300 KV脉冲重复频率下正常工作.测量结果表明,在100 KV脉冲重频时该脉冲发生器可以输出一对峰峰值为230 V、前沿为1.3 ns的平衡脉冲,并有着极小的振铃和过冲.这些特征说明,该脉冲发生器在探地雷达应用中有着更深探测距离和更快数据处理速度的优势.     

A CCII‐based wide frequency range square waveform generator

In this paper, we propose a novel current‐mode solution suitable for the square waveform generation. The designed oscillator, which utilizes only two positive second‐generation current conveyors as active blocks, six resistors and a capacitor, is based on a current differentiation, instead of voltage integration, typical of developed solutions both in voltage‐mode and in current‐mode approaches, so avoiding circuit limitations due to the node saturation effects. The proposed circuit has been designed, as an integrated solution at transistor level, in a standard CMOS technology, with low‐voltage (± 1V) and low‐power (430µW) characteristics. Simulation results have confirmed the good circuit behaviour, also for working temperature drifts, showing good linearity in a wide oscillation frequency range, which can be independently adjusted through either capacitive (in the range pF ? µF) or resistive (in the range M Ω–G Ω) external passive components. Waiting for the chip fabrication, preliminary measurements have been performed using a laboratory breadboard employing the CCII with AD844 commercial component and sample capacitors and resistors. The experimental results have shown good agreement with both simulations and theoretical expectations. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques is proposed in this article. The benefits of the accelerated pulse‐width‐modulation technique is fast‐transient response, simple‐compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage‐mode speed is slower with the transient response, so an accelerated pulse‐width‐modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm². Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley & Sons, Ltd.     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.