Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis,design, and optimization based on settling time

In analog signal‐processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low‐voltage environment of modern technologies where only a few transistors are allowed to be stacked, three‐stage amplifiers are gaining more interest. Unfortunately, design and optimization of three‐stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed‐form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three‐stage nested‐Miller‐compensated opamps, including linear and non‐linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm². Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.     

An approach to model high‐frequency distortion in negative‐feedback amplifiers

In this paper, we present an analytical approach to study the harmonic distortion in the frequency domain of operational amplifiers (opamps) embedded in a nonlinear feedback network. The analysis is based on a frequency‐domain block scheme that models the opamp with one block and the feedback network with two blocks, but it is demonstrated that only one feedback block needs to be characterized for the two basic inverting and non‐inverting configurations. The obtained closed‐form expressions extend our understanding of nonlinear frequency behaviour in feedback opamp circuits. Indeed, they give the contribution of each network component to the output distortion. As an instructive example, we analysed second‐ and third‐order harmonic distortion of an active‐RC inverting lossy integrator having all the components nonlinear. The accuracy of the proposed method is confirmed by comparison with computer simulations at transistor level. Copyright © 2006 John Wiley & Sons, Ltd.     

A class of digitally programmable nth‐order filters

A family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.     

Current‐mode filters based on current mirror arrays

A technique is proposed for obtaining current‐mode filters based on current mirror arrays that operate as unity gain current amplifiers. These amplifiers by properly driving capacitors realize active lossless integrators which are the basic active elements for the derivation of filters according to the leapfrog method. Due to the fact that both the structure of the amplifiers and the adapted method for filter design are simple, the proposed technique is attractive for filter design and implementation. A design and the implementation of two third‐order low‐pass filters are presented. The array of the amplifiers has been implemented in a 0.8 µm CMOS technology. Copyright © 2007 John Wiley & Sons, Ltd.     

Design methodology for common‐mode stability of OTA‐based gyrators

This paper presents a design methodology for common‐mode (CM) stability of operational transconductance amplifier (OTA)‐based gyrators. The topology of g_m ? C active inductors is briefly reviewed. Subsequently, a comprehensive mathematical analysis on the CM stability of OTA‐based gyrators is presented. Sufficient requirements for the gyrator's CM stability, which easily can be considered during the design process of common‐mode feedback (CMFB) amplifiers, are defined. Based on these stability requirements, a design methodology and a design procedure are proposed. Finally, in order to validate the proposed procedure, a resonator with 20 MHz resonance frequency and a quality factor of 20 is fabricated with UMC 180 nm complementary metal‐oxide‐semiconductor technology, and its CM stability is examined. Copyright © 2015 John Wiley & Sons, Ltd.     

Robust design of CMOS amplifiers oriented to settling‐time specification

In this paper, we propose a new approach for the robust design of complementary metal‐oxide‐semiconductor amplifiers based on settling‐time specifications. The approach is based on the definition of the separation factors and on the analysis of their role in the settling time. We define a design strategy for being certain that an OTA satisfies the settling‐time constraint under any statistical variation of process or design parameters. The proposed strategy is applied to the transistor level design of a two‐stage amplifier and a three‐stage one. Simulation results, in good agreement with theory, confirm the validity of the proposed approach. Copyright © 2016 John Wiley & Sons, Ltd.     

Bessel‐like compensation of three‐stage operational transconductance amplifiers

In this paper, we introduce a simple and well‐defined approach for the design of fast settling amplifiers suitable for switched‐capacitor circuits and characterized by low capacitive loads, in the order of few pico‐farad. In the specific, the design is based on a new Bessel‐like compensation that sets the phase of the closed‐loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The proposed Bessel‐like approach is validated through the design and the simulation of two 3‐stage amplifiers in a 65‐nm CMOS process.     

Single Miller capacitor frequency compensation with nulling resistor for three‐stage amplifiers

A frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor. The dc consumption is about 14µA at DC and a 1.8‐MHz gain–bandwidth product is obtained, providing significant improvement in both (MHzpF)/mA and ((V/µs)pF)/mA performance parameters. Copyright © 2007 John Wiley & Sons, Ltd.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

This paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.     

Efficient generation of compact symbolic network functions in a nested rational form

This paper presents the extension of generalized parameter extraction method for direct circuit function generation in a fully symbolic form of rational expressions or a nested s-expanded polynomial. The new formula for implicit extraction of parameters that allows effective factoring by grouping of determinants of circuits containing any linear models of active elements, such as controlled sources, nullors, and pathological mirrors, is proposed. The concept of nullor with parameter is used for implicit extraction. The rules of optimal selection of parameters for extraction are presented. The proposed algorithm of symbolic analysis is implemented in the CirSym program, which is available online. The paper discusses the results of automatic analysis of several large active circuits, as well as determinants of matrixes and passive topologies, in terms of compact size and minimization of the number of arithmetic operations. Experimental results demonstrate that the expressions of determinants derived by CirSym are more compact than the results of the factorization algorithms of commercial computer algebra systems. The comparison with several other symbolic analysis algorithms shows that CirSym is the only available program that provides the exact calculation of the symbolic function of large circuits in the s-expanded form with every coefficient being a compact-nested expression.     

Transistor‐level optimization methodology for the complete design of switched‐capacitor filter circuits

This paper presents an automatic procedure for the design and optimization of switched‐capacitor (SC) filters, including the automatic sizing of transistors in the amplifiers and switches. The optimization procedure is based on genetic algorithms (GAs) where the circuit's fitness is first computed using equations describing the filter's transfer function and then using transient simulations. These equations are obtained using a fast numerical methodology that takes into consideration the electrical behavior of all components in the circuit. The poles and zeros of the SC filter's transfer function are computed using a system of differential equations, obtained from the inspection of the circuit. This system describes the filter's behavior for all switch combinations, including the non‐ideal effects of the transistors in the switches and amplifiers. Due to the low computational effort and accuracy of this methodology, it is possible to use a large population in the GA. After finding a solution through equations, the more computationally intensive SPICE transient simulations are used to fine‐tune the solution, with a much smaller population in the GA. Taking advantage of the equations' low computational load and accuracy, process, voltage, temperature (PVT) corners and mismatch errors optimizations are also performed, allowing the chromosomes fitness to be calculated taking into consideration multiple cases, thus resulting in a low sensitivity design.     

A methodology to design continuous‐time adaptive equalizers

Serial communications systems suffer from channel bandwidth limitations that result in eye closure and inter‐symbol interference. Adaptive equalization at the receiver is widely implemented to alleviate this, and a number of continuous‐time techniques aiming multi‐gigabit operation have been proposed. The operation of adaptive equalizers is based on signal filtering carried out by loop filters whose characteristics are usually given ad‐hoc after a trial and error process. This paper presents a unified analysis of the operation of continuous‐time adaptive equalizers that results in a general design methodology to select the frequency characteristics of the filters implemented in the adaptation loop. Using the proposed methodology, a novel adaptation loop filter combination incorporating two low‐pass filters is presented. Copyright © 2016 John Wiley & Sons, Ltd.     

Calculating the optimal optical ultra-long haul network

Today's new generation of undersea cable systems extensively uses optical amplifiers, which allows the systems to be implemented over transoceanic distances. Optical amplifiers offer significantly increased transmission capacity, networking functionality and operational flexibility - all potentially at lower cost than traditional regeneration systems. Thus, similar techniques are now being used in terrestrial networks to exploit the wide bandwidth of optical fibers for long-distance transmission (thousand of miles) since the frequency range is in THz. A network optimization design methodology for ultra-long-haul terrestrial networks is presented and a variety of network architectures analyzed: optical networks with a 1:N path restoration mechanism; optical networks with express routes and a 1:N path restoration; line shared protection ring (LSPR) networks. This methodology is applied to an example network using several traffic scenarios. The optimal network architecture depends on the network itself and on the criteria determining the network design.     

A method for acceptability region representation in analogue linear networks

A new simple approach to acceptability region representation in analogue linear circuit design is presented. The proposed method is also able to characterize non‐convex and disjoint acceptability regions with low computational effort. In fact, the developed procedure is based on the use of symbolic analysis techniques, which permit one to perform only one simulation of the circuit under consideration, thus reducing the computational efforts. The theoretical basis and the algorithm implementing the technique are presented. A circuital example is also included. Copyright © 2008 John Wiley & Sons, Ltd.     

Set theoretic performance verification of low‐frequency learning adaptive controllers

Although adaptive control has been used in numerous applications, the ability to obtain a predictable transient and steady‐state closed‐loop performance is still a challenging problem from the verification and validation standpoint. To that end, we considered a recently developed robust adaptive control methodology called low‐frequency learning adaptive control and utilized a set of theoretic analysis to show that the transitory performance of this approach can be expressed, analyzed, and optimized via a convex optimization problem based on linear matrix inequalities. This key feature of this design and analysis framework allows one to tune the adaptive control parameters rigorously so that the tracking error components of the closed‐loop nonlinear system evolve in a priori specified region of the state space whose size can be minimized by selecting a suitable cost function. Simulation examples are provided to demonstrate the efficacy of the proposed verification and validation architecture showing the possibility of performing parametric studies to analyze the interplay between the size of the tracking error residual set and important design parameters such as the adaptation rate and the low‐pass filters time constant of the weights adaptation algorithm. Copyright © 2014 John Wiley & Sons, Ltd.     

Semi‐analytical non‐charge‐sheet and non‐depletion MOS model,for inversion charge calculation

A new computationally implemented semi‐analytic mathematical model is presented to obtain a more accurate estimation of the inversion charge in a MOS structure than standard models. The values of the error of the inversion charge obtained are compared with the assumed ‘exact’ numerical calculated values. These errors are appreciably smaller than the estimation coming from the classical charge‐sheet and depletion approximations. Also the calculation time to obtain the inversion charge is shown to be significantly lower than the numerical one. Because of its accuracy and its relatively low computational speed, the proposed model is a good alternative methodology for the calculation of the inversion charge of MOSFET transistors as a function of their physical features and gate bias voltage. In this sense it should be very useful to be implemented by computer‐aided design integrated circuit simulation software. Copyright © 2013 John Wiley & Sons, Ltd.