Feed models for coax-driven monopole and dipole antennas

A method is presented for accurately modeling a monopole or dipole antenna fed by a coaxial line. The base of the monopole is attached to a conducting plane through which the coaxial feed line extends to the feed. The feed structures considered are easily adaptable to physically rugged forms and are simple to construct. Equivalent models for the three regions of the structure are devised and coupled integral equations for aperture fields and surface currents are formulated to enforce the boundary conditions. Three variations of the feed configuration are discussed and the reflection coefficient of the antenna feed is determined from the data obtained from the solutions of the coupled integral equations. Computed reflection coefficient values are shown to agree well with values measured on laboratory models.     

Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.     

On a More Accurate Assessment of Scaled Copper/Low-k Interconnects Performance

Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity (rho_Cu), is an important performance metric for back-end-of-line (BEOL) process assessment. As process technology scales, interpretation of fundamental process-induced RC delay variations becomes a challenge as the relative importance of statistical process-induced fluctuations (variation of critical dimensions during plasma etching of low-k materials, line profiles, thickness nonuniformity, etc.) grows rapidly and begins to show. A more accurate interpretation of experimental data and prediction of future performance trends requires a more realistic assessment that accounts for such statistical fluctuations. In this paper, an inventory of the most common possible sources of statistical process-induced RC delay variations is made, parameterized, and subsequently used to generate a realistic 2-D interconnect model from which, R and C, and thereby RC delay, are computed. For both wire resistivity and RC, response surface models (RSM) are subsequently generated based on the results of a full factorial design-of-experiment analysis with these input parameters. Finally, based on the RSMs, an improved methodology of interconnect performance evaluation is proposed.     

A knowledge-based system for protocol synthesis (KSPS)

A knowledge-based system for protocol synthesis named KSPS is presented. The aim of KSPS is to help the protocol designer design a protocol without logical errors, such as unspecified receptions and state deadlocks. KSPS consists of three major components: a knowledge base, a user interface, and an inference engine. The construction of the knowledge base and the user interface is examined. The knowledge of protocol synthesis represented in the production model and in the procedure programming model is embedded in the knowledge base. A user-friendly interface with a multiwindow mechanism is designed which provides the graphic tools in this system. Consequently, the protocol designer without experience in protocol synthesis can easily design a protocol without logical errors     

An optical holographic backplane interconnect system

An optical holographic backplane interconnect system capable of high-speed information transmission between optoelectronic transmitter/receiver boards is described. Using conjugate pairs of transmission gratings in a folded reflection geometry, a practical method of insulating the interconnect system from wavelength variations due to temperature or power fluctuations can be achieved. The final demonstration unit was developed in a fully packaged form and has the potential for reconfigurable interconnects and may serve as a testbed for a variety of interconnect networks and hardware protocols     

考虑工艺波动的RLC互连延时统计模型

基于概率解释算法的原理,提出了一种考虑工艺波动的RLC互连延时统计模型,该模型使用了对数正态分布函数。在给定互连参数波动范围条件下,利用该算法计算延时仅需要采用前两个瞬态。和HSPICE相比,Monte Carlo分析中的均值和平均偏差误差分别低于0.7％和0.51％。模型计算简单且精度高,可以满足互连线仿真要求。     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of design. It is illustrated in this paper that the WPM network can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Both, a system level analysis and circuit level verification of this WPM routing are presented in this paper. A multilevel interconnect network design simulator (MINDS) that uses system level interconnect prediction (SLIP) techniques and HSPICE circuit simulations for optimizing the interconnect dimensions has been used to assess the opportunities for application of WPM wire circuits in high performance digital designs. A custom routing example highlights the ease with which the WPM routing technique can be easily incorporated into the existing VLSI systems. In addition, for a 40 million transistor system case study, this system level analysis reveals that the use of a WPM network could result in an almost 20% decrease in the number of metal layers for less than 4% increase in dynamic power with no loss of communication throughput performance. The key virtues of WPM routing are its flexibility, robustness, implementation simplicity and its low overhead requirements.     

On the frequency-dependent line admittance of VLSI interconnect lines on silicon-based semiconductor substrates

In this paper, a method for analysis and modelling of transmission interconnect lines with zero- or non-zero thickness on Si–SiO₂ substrate is presented. The analysis is based on semi-analytical expressions for the frequency-dependent transmission line admittances. The electromagnetic concept of free charge density is applied. It allows us to obtain integral equations between electric scalar potential and charge density distributions. These equations are solved by the Galerkin procedure of the method of moments. This new model represents narrow and thick line interconnect behaviour over a wide range of frequencies up to 20 GHz. The accuracy of the developed method in this work is validated by comparing with the rigorous simulation data obtained by full-wave electromagnetic solver and CAD-oriented equivalent-circuit modelling approach. The response of the proposed model is shown to be in good agreement with the frequency-dependent capacitance and conductance characteristics of general coupled multiconductor on-chip interconnects.     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

Integrated interconnect networks for RF switch matrix applications

In this paper, two new types of integrated RF interconnect networks are presented. The circuits are printed on double-sided alumina substrates, eliminating the need to use multilayer manufacturing technology. The interconnect networks employ finite ground coplanar lines and vertical transitions and can be easily integrated with semiconductor and microelectromechanical-systems switches. A wide-band 3/spl times/3 interconnect network utilizing single and double three-via vertical transitions is investigated theoretically and experimentally. The measured results show a return loss of -20dB and an isolation of better than -40dB up to 30 GHz. A vialess double-sided interconnect network is also studied and optimized for satellite Ku-band applications. This type of interconnect network uses a process requiring only front and back pattern metallization. The measured results indicate a return loss of better than -17dB and an isolation of better than -45dB.     

Efficient bit-serial multiplication and the discrete-timeWiener-Hopf equation over finite fields

Discrete-time Wiener-Hopf equations (DTWHEs) over finite fields are considered. It is shown that solving the DTWHE is equivalent to performing division over finite fields. The proof provides a new interpretation of the relationship between bit-serial multiplication and DTWHEs. The interpretation enables bit-serial multiplication over GF(2 ^m) to be understood more easily. As an example, bit-serial multiplication methods for multiplying any two elements that can be done without performing any transformation, or with only a simple transformation of the bases, are presented     

Circuit sensitivity to interconnect variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations     

Switching Activity Minimization in Iterative LDPC Decoders

LDPC codes can be designed to perform extremely close to the Shannon limit. Achieving such performance with high energy efficiency is now a main goal in the research community. This work combines knowledge of LDPC decoder message statistics, provided by density evolution, with knowledge of the physical implementation of decoders to predict switching activity in the decoder interconnect. In this work we provide results for the switching activity on the interconnect for fully parallel decoders. However, our model can be applied to partially parallel and serial implementations, and is not limited to interconnect. It is shown that switching activity can vary by as much as 300%, depending on several hardware design choices. Results of this work validate the usefulness of the presented model for providing designers with an understanding of how their decoder implementation choices affect power consumption for any size of LDPC code. This knowledge can be used for making design choices that minimize decoder power consumption very early in the hardware design process.     

Bayes estimation of component-reliability from masked system-lifedata

This paper estimates component reliability from masked series-system life data, viz, data where the exact component causing system failure might be unknown. It focuses on a Bayes approach which considers prior information on the component reliabilities. In most practical settings, prior engineering knowledge on component reliabilities is extensive. Engineers routinely use prior knowledge and judgment in a variety of ways. The Bayes methodology proposed here provides a formal, realistic means of incorporating such subjective knowledge into the estimation process. In the event that little prior knowledge is available, conservative or even noninformative priors, can be selected. The model is illustrated for a 2-component series system of exponential components. In particular it uses discrete-step priors because of their ease of development and interpretation. By taking advantage of the prior information, the Bayes point-estimates consistently perform well, i.e., are close to the MLE. While the approach is computationally intensive, the calculations can be easily computerized     

WLAN chip antenna mountable above the system ground plane of a mobile device

A novel wireless local-area network (WLAN) chip antenna suitable to be mounted above the system ground plane of a mobile device is presented. The antenna in the study is easily fabricated from folding a single metal plate onto a foam base, and mainly comprises a short-circuited radiating strip and an antenna ground. The antenna ground occupies the bottom surface and two adjacent side surfaces of the foam base. When the antenna is mounted at the corner of the system ground plane, this antenna ground structure is expected to effectively reduce the antenna's possible fringing electromagnetic fields inside the mobile device. In this case, when the associated element such as the radio-frequency shielding metal case is placed under the proposed antenna, small or negligible variations in the antenna performance are obtained. Design considerations of the proposed antenna for WLAN operation in the 2.4 GHz band are described, and results of the constructed prototypes are presented.     

On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect

Bundles of single-walled carbon nanotubes (SWCNTs) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current-carrying capabilities. Given the manufacturing challenges associated with future nanotube-based interconnect solutions, determining the impact of process variations on this new technology relative to standard copper interconnect is vital for predicting the reliability of nanotube-based interconnect. In this paper, we investigate the impact of process variations on future interconnect solutions based on carbon nanotube bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall three-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by up to 63% in 22-nm process technology     

A Dyadic Green's Function Based Method for the Transient Analysis of Lossy and Dispersive Multiconductor Transmission Lines

This paper describes a new algorithm for the analysis of multiconductor transmission lines characterized by frequency-dependent per-unit-length parameters. The proposed model is based on studying telegrapher's equations as a Sturm-Liouville problem. The open-end impedance matrix is expressed in a series form as an infinite sum of matrices of rational functions, derived from the series form of the dyadic Green's function. The rational form of the open-end impedance matrix allows an easy identification of poles and residues and, thus, the development of a reduced-order system of the interconnect. The pole-residue representation can be synthesized in an equivalent circuit or converted into a state-space model, which can be easily embedded into conventional nonlinear circuit SPICE-like solvers. The numerical results confirm the validity of the proposed modeling technique.     

On the two-dimensional capacitance calculation of multiconductor multilayered interconnects

In this paper a method for analysis and modelling of transmission interconnect lines on multilayered dielectric media is presented. The analysis is based on semianalytical layered Green’s function and the electromagnetic concept of free charge density. It allows us to obtain integral equations between electric scalar potential and charge density distributions. These equations are solved by the Galerkin procedure of the Method of Moments. After this, the capacitance matrix of multiconductor interconnect lines in the presence of planar dielectric interfaces is calculated. When there exists no infinite ground plane, we enforce the constraint that the sum of all free charges is zero. The feasibility of the method has been shown by simulations of several transmission-line problems. The results have been compared with reported data obtained by free-space Green’s function method, conformai mapping formulas, generalized method of lines and inverted capacitance coefficient matrix technique. The proposed approach is not inferior to other procedures in terms of generality and memory requirements. At the same time, a reduction of the central processing unit (cpu) time is achieved because the integral equations are solved numerically only on the surface of conductor lines.     

Three-dimensional magnetotelluric modelling and inversion

An outline is presented of the nature of the problem of making quantitative use of magnetotelluric data for geophysical exploration. The authors discuss their view and experiences in dealing with the modeling and interpretation problems. The key step is considered to be the modeling step, which is that of predicting the response of a given distribution of electrical properties within the Earth to the electromagnetic excitation. Decisions about modeling methods also consider the interpretation process that will be used. The electromagnetic problem is three-dimensional which makes it necessary to use numerical methods. Difference equations are used and the authors investigate spacing requirements and two approaches to solving the system of equations: a relaxation method and a direct solution method. The relaxation method is found to be much faster, but it is very difficult to eliminate all the errors in the resulting solution. The interpretation problem is approached using a scheme that minimizes the joint probability of fitting the observed data and adhering to an a priori conductivity model. A relaxation procedure is used to solve this problem and the behavior of the procedure is examined associated with the application of magnetotellurics to exploration problems. Some of the problems in signal resolution that arise when interpreting the data are noted