SOA-Based Ultrafast Multifunctional All-Optical Logic Gates With PolSK Modulated Signals

In this paper, we propose a novel scheme for ultrafast multifunctional all-optical logic gates, which can achieve not only simple logic gates including AND, NOR, $ {S_{1}}{bar S_{2}} $, $ {bar S_{1}}{S_{2}} $, XNOR, and XOR but also complex logic gates including half adder, half subtracter, decoder, and comparer based on four-wave mixing in semiconductor optical amplifiers (SOAs) with polarization-shift-keying (PolSK) modulated signals. A comprehensive polarization-dependent broadband dynamic model of this kind of ultrafast multifunctional all-optical logic gates is presented. By numerical simulation, the multifunctional all-optical logic gates are theoretically realized at 40 Gbit/s. The effects of two input signal powers, injected current, frequency detuning, and polarization dependence of SOA on the output performance of the multifunctional all-optical logic gates are theoretically investigated in detail. The results indicate that this scheme is free of pattern effect due to using the PolSK modulation format. Moreover, the nice eye opening of the logic gates indicates the good performance of the proposed ultrafast multifunctional all-optical logic gates. This scheme is potential for applications in future high bit rate optical networks.      

Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements

With clock frequencies in the multigigahertz range, wide wires in the power and clock distribution networks suffer from prominent frequency-dependent effects. To overcome the simulation problem of such circuits, a guaranteed stable and parallelizable model order reduction technique is proposed that can handle frequency-dependent elements by construction. The basic idea is to match the output at multiple frequencies with a reduced order function. Once the reduced function is known, it becomes straightforward to calculate the time-domain response. Since this technique works in the frequency domain, it does not require replacement of frequency-dependent elements with equivalent constant RLC subcircuits, significantly reducing the size of equivalent circuits of wide power and clock distribution networks. With parallel computation, the proposed technique obtains time-domain responses in comparable time to calculate the first moment in AWE. Simulations have shown that as few as six frequency points are needed for coupled RC circuits and up to 50 frequency points are needed for complex RLC circuits. To test its ability of handling frequency-dependent elements, a sample circuit with frequency-dependent elements is used that is about 30% of the size of the equivalent circuit with constant RLC elements used in SPICE. In all cases, the proposed technique gives accurate and stable time-domain responses.      

Universal Lossless Compression of Erased Symbols

A source ${mmb X}$ goes through an erasure channel whose output is ${mmb Z}$. The goal is to compress losslessly ${mmb X}$ when the compressor knows ${mmb X}$ and ${mmb Z}$ and the decompressor knows ${mmb Z}$. We propose a universal algorithm based on context-tree weighting (CTW), parameterized by a memory-length parameter $ell$. We show that if the erasure channel is stationary and memoryless, and ${mmb X}$ is stationary and ergodic, then the proposed algorithm achieves a compression rate of $H(X_0vert X_{-ell}^{-1}, Z^ell)$ bits per erasure.      

Properties and Applications of Preimage Distributions of Perfect Nonlinear Functions

The preimage distributions of perfect nonlinear functions from an Abelian group of order $n$ to an Abelian group of order $3$ or $4$, respectively, are studied. Based on the properties of the preimage distributions of perfect nonlinear functions from an Abelian group of order $3^{r}$ to an Abelian group of order $3$, the weight distributions of the ternary linear codes $C_{Pi}$ from the perfect nonlinear functions $Pi (x)$ from $F_{3^{r}}$ to itself are determined. These results suggest that two open problems, proposed by Carlet, Ding, and Yuan in 2005 and 2006, respectively, are answered.      

Robust Precoder Adaptation for MIMO Links With Noisy Limited Feedback

In this paper, we propose two robust limited feedback designs for multiple-input multiple-output (MIMO) adaptation. The first scheme, namely, the combined design jointly optimizes the adaptation, CSIT (channel state information at the transmitter) feedback as well as index assignment strategies. The second scheme, namely, the decoupled design, focuses on the index assignment problem given an error-free limited feedback design. Simulation results show that the proposed framework has significant capacity gain compared to the naive design (designed assuming there is no feedback error). Furthermore, for large number of feedback bits $C_{rm fb}$, we show that under two-nearest constellation feedback channel assumption, the MIMO capacity loss (due to noisy feedback) of the proposed robust design scales like ${cal O}(P_e2^{-{{C_{rm fb}}over{t+1}}})$ for some positive integer $t$. Hence, the penalty due to noisy limited feedback in the proposed robust design approaches zero as $C_{rm fb}$ increases.      

On the Values of Kloosterman Sums

Given a prime $p$ and a positive integer $n$ , we show that the shifted Kloosterman sums $$sum _{x in BBF _{p^{n}}} psi (x + ax^{p^{n}-2}) = sum _{xin BBF _{p^{n}}^{ast }} psi(x + ax^{-1}) + 1, quad a inBBF _{p^{n}}^{ast }$$ where $psi$ is a nontrivial additive character of a finite field $BBF _{p^{n}}$ of $p^{n}$ elements, do not vanish if $a$ belongs to a small subfield $BBF_{p^{m}} subseteq BBF _{p^{n}}$. This complements recent results of P. Charpin and G. Gong which in turn were motivated by some applications to bent functions.      

High-Temperature High-Power Operation of GaInNAs Laser Diodes in the 1220–1240-nm Wavelength Range

We report on the high-temperature performance of high-power GaInNAs broad area laser diodes with different waveguide designs emitting in the 1220–1240-nm wavelength range. Large optical cavity laser structures enable a maximum continuous-wave output power of $>$8.9 W at ${T}=20 ^{circ}$C with emission at 1220 nm and are characterized by low internal losses of 0.5 cm$^{-1}$ compared to 2.9 cm$^{-1}$ for the conventional waveguide structures. High-power operation up to temperatures of 120 $^{circ}$C is observed with output powers of $>$4 W at ${T}=90 ^{circ}$C. This laser diode showed characteristic temperatures of ${T}_{0} =112$ K and ${T}_{1}=378$ K.      

Single-Exclusion Number and the Stopping Redundancy of MDS Codes

For a linear block code ${cal C}$, its stopping redundancy is defined as the smallest number of check nodes in a Tanner graph for ${cal C}$, such that there exist no stopping sets of size smaller than the minimum distance of ${cal C}{bf .},$ Schwartz and Vardy conjectured that the stopping redundancy of a maximum-distance separable (MDS) code should only depend on its length and minimum distance.      

Logarithmic Sobolev Inequalities for Information Measures

For $alphageq 1$, the new Vajda-type information measure ${bf J}_{alpha}(X)$ is a quantity generalizing Fisher's information (FI), to which it is reduced for $alpha=2$ . In this paper, a corresponding generalized entropy power ${bf N}_{alpha}(X)$ is introduced, and the inequality ${bf N}_{alpha}(X) {bf J}_{alpha}(X)geq n$ is proved, which is reduced to the well-known inequality of Stam for $alpha=2$. The cases of equality are also determined. Furthermore, the Blachman–Stam inequality for the FI of convolutions is generalized for the Vajda information ${bf J}_{alpha}(X)$ and both families of results in the context of measure of information are discussed. That is, logarithmic Sobolev inequalities (LSIs) are written in terms of new more general entropy-type information measure, and therefore, new information inequalities are arisen. This generalization for special cases yields to the well known information measures and relative bounds.      

On the Capacity of Ad Hoc Networks Under Random Packet Losses

We consider the problem of determining asymptotic bounds on the capacity of a random ad hoc network. Previous approaches assumed a link layer model in which if a transmitter-receiver pair can communicate with each other, i.e., the signal to interference and noise ratio (SINR) is above a certain threshold, then the transmitted packet is received error-free by the receiver thereby. Using this model, the per node capacity of the network was shown to be $Theta left ( {{ 1}over { sqrt {nlog {n}}}}right )$. In reality, for any finite link SINR, there is a nonzero probability of erroneous reception of the packet. We show that in a large network, as the packet travels an asymptotically large number of hops from source to destination, the cumulative impact of packet losses over intermediate links results in a per-node throughput of only $Oleft ( {{ 1}over { n}}right )$ under the previously proposed routing and scheduling strategy. We then propose a new scheduling scheme to counter this effect. The proposed scheme provides tight guarantees on end-to-end packet loss probability, and improves the per-node throughput to $Omega left ( {{ 1}over { sqrt {n} left ({log {n}}right )^{{ alpha {+2}}over { 2(alpha -2)}}}}right )$ where $alpha >2$ is the path loss exponent.      

CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-$mu$m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.      

Current-Mode Phase-Locked Loops With CMOS Active Transformers

This paper introduces active transformer current- mode phase-locked loops (PLLs). The proposed PLLs replaces the RC loop filter of voltage-mode PLLs with an active transformer loop filter to take the advantage of their large inductance and small silicon area. A current-controlled LC oscillator with active inductors is employed to further reduce silicon area. The sensitivity of the cutoff frequency of active transformer loop filter to supply voltage fluctuation and process variation is analyzed. A 3-GHz PLL has been implemented in TSMC 0.18- $mu$m 6-metal 1.8-V CMOS technology and analyzed using SpectreRF with BSIM3v3 device models and Verilog-AMS from Cadence Design Systems. The lock time of the PLL is 60 ns. The power consumption and phase noise of the PLL are 16 mW and ${-}$100 dBc/Hz at 1-MHz frequency offset, respectively. The layout area of the PLL is 2800 $mu hbox{m}^2$.      

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration

We present an area-efficient method and field-programmable gate array (FPGA) realization for two common operations in robotics, namely, the following: 1) rotating a vector in 2-D and 2) aligning a vector in the plane with a specific axis. It is based on a new coordinate rotation digital computer (CORDIC) algorithm that is designed to work with a small set of elementary angles. Unlike conventional CORDIC, the proposed algorithm does not require a ROM and a full-fledged barrel shifter. The proposed CORDIC algorithm is used to design hardware-efficient solutions for two mobile robotic tasks in an indoor environment without employing division and floating-point calculations. Experiments with a sole low-end FPGA-based robot in static as well as dynamic environments validate the power of the approach.      

Sharp $p$ -Divisibility of Weights in Abelian Codes Over ${BBZ}/p^d{BBZ}$

A theorem of McEliece on the $p$-divisibility of Hamming weights in cyclic codes over ${BBF}_p$ is generalized to Abelian codes over ${{{BBZ}/p^d{BBZ}}}$. This work improves upon results of Helleseth–Kumar–Moreno–Shanbhag, Calderbank–Li–Poonen, Wilson, and Katz. These previous attempts are not sharp in general, i.e., do not report the full extent of the $p$ -divisibility except in special cases, nor do they give accounts of the precise circumstances under which they do provide best possible results. This paper provides sharp results on $p$-divisibilities of Hamming weights and counts of any particular symbol for an arbitrary Abelian code over ${{{BBZ}/p^d{BBZ}}}$. It also presents sharp results on $2$-divisibilities of Lee and Euclidean weights for Abelian codes over ${{{BBZ}/4{BBZ}}}$.      

Finite State Channels With Time-Invariant Deterministic Feedback

We consider capacity of discrete-time channels with feedback for the general case where the feedback is a time-invariant deterministic function of the output samples. Under the assumption that the channel states take values in a finite alphabet, we find a sequence of achievable rates and a sequence of upper bounds on the capacity. The achievable rates and the upper bounds are computable for any $N$, and the limits of the sequences exist. We show that when the probability of the initial state is positive for all the channel states, then the capacity is the limit of the achievable-rate sequence. We further show that when the channel is stationary, indecomposable, and has no intersymbol interference (ISI), its capacity is given by the limit of the maximum of the (normalized) directed information between the input $X^{N}$ and the output $Y^{N}$ , i.e., $$C = lim _{N rightarrow infty } {{ 1}over { N}} max I(X^{N} rightarrow Y^{N} )$$ where the maximization is taken over the causal conditioning probability $Q(x^{N}Vert z^{N-1})$ defined in this paper. The main idea for obtaining the results is to add causality into Gallager's results on finite state channels. The capacity results are used to show that the source–channel separation theorem holds for time-invariant determinist feedback, and if the state of the channel is known both at the encoder and the decoder, then feedback does not increase capacity.      

Nonlinear Influence of T-Channels in an in silico Relay Neuron

Thalamic relay cells express distinctive response modes based on the state of a low-threshold calcium channel (T-channel). When the channel is fully active (burst mode), the cell responds to inputs with a high-frequency burst of spikes; with the channel inactive ( tonic mode), the cell responds at a rate proportional to the input. Due to the T-channel's dynamics, we expect the cell's response to become more nonlinear as the channel becomes more active. To test this hypothesis, we study the response of an in silico relay cell to Poisson spike trains. We first validate our model cell by comparing its responses with in vitro responses. To characterize the model cell's nonlinearity, we calculate Poisson kernels, an approach akin to white noise analysis but using the randomness of Poisson input spikes instead of Gaussian white noise. We find that a relay cell with active T-channels requires at least a third-order system to achieve a characterization as good as a second-order system for a relay cell without T-channels.      

Managing Information Technology Project Escalation and De-Escalation: An Approach-Avoidance Perspective

This paper presents an integrated theoretical process model for identifying , describing, and analyzing the complex escalation and de-escalation phenomena in software development projects. The approach-avoidance theory is used to integrate core elements of various escalation theories into a holistic, explanatory framework for the two phenomena. We use a process model to identify antecedent conditions, sequences of events, critical incidents, and outcomes over the course of a project. The analysis also operates at multiple levels: project, work, and environment. This highlights the recursive interactions between project, organizational work activities, and their contexts during the software project development process. By conceiving the processes of commitment escalation and de-escalation as sequences of events involving recurring approach-avoidance decision conflict, this research allows for a deeper understanding of the ambiguity and dilemma that decision makers face during project escalations and de-escalations. Our proposed model was both informed by a detailed case study that exhibits both project escalation and de-escalation conditions, and at the same time, illuminates the perspectives of various stakeholders.      

Weil-Serre Type Bounds for Cyclic Codes

We give a new method in order to obtain Weil-Serre type bounds on the minimum distance of arbitrary cyclic codes over ${BBF}_{p^e}$ of length coprime to $p$, where $e ge 1$ is an arbitrary integer. In an earlier paper we obtained Weil-Serre type bounds for such codes only when $e=1$ or $e=2$ using lengthy explicit factorizations, which seems hopeless to generalize. The new method avoids such explicit factorizations and it produces an effective alternative. Using our method we obtain Weil–Serre type bounds in various cases. By examples we show that our bounds perform very well against Bose–Chaudhuri–Hocquenghem (BCH) bound and they yield the exact minimum distance in some cases.      

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66$times$ average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-$mu$ m process.