大规模集成电路的可靠性与失效机理

本文在介绍了大规模集成电路可靠性重要意义的基础上,阐明影响其可靠性的若干因素。并着重研究和分析了大规模集成电路尤其是超大规模集成电路的失效机理。     

超净技术

超大规模集成电路与大规模集成电路在结构及工艺方面没有多大差别,即使在制造技术上超大规模集成电路部分地采用了电子束曝光及干法工艺等新技术,但在制作方式上与大规模集成电路基本上没有什么不同。因此,在超大规模集成电路制作工艺过程中,所使用的净化间方面并不一定会出现特别新的问题,它与目前大规模集成电路制作工艺过程中所使用的净化间     

超大规模集成电路的作用及展望

本文阐述了初级集成电路至超大规模集成电路的发展概况,介绍了大规模集成电路在通讯、控制系统、信息系统中的应用。还扼要地叙述了大规模集成电路对设备安装技术的影响,且对其在未来的通讯网中将起到越来越大的作用作了恰当的估计及展望。     

硅器件钝化工艺的进展

一、前言 钝化是改善器件性能和提高可靠性所不可缺少的手段,也是硅工艺中酌一个重点。在当前发展以MOS为主的大规模(LSI)和超大规模(VLSI)集成电路中,其重要性就更加无可非议。 硅器件的钝化,自有平面器件以来,已有广泛而系统的研究,发表了大量文章,目前不管在理论认识上还是在实际技术上,都达到了可观的水平,成为硅器件继续向超大规模集成电路迈进的一个重要基础。本文就硅器件钝化     

掩模自动检查系统提高了大规模集成电路的成品率、性能和可靠性

在日本,大规模集成电路光刻掩模的缺陷自动检查,现已成为不可缺少的事了。掩模缺陷自动检查设备是四前年投入实际使用的,它的迅速普及已使人们能用到优质的光刻掩模。进而,这又大大提高了大规模集成电路的性能,可靠性和生产成品率。近来,用常规光刻掩模制造高集成度集成电路——超大规模集成电路的可能性也终于得到证实。     

超大规模集成技术

一、什么是超大规模集成电路所谓超大规模集成电路是指集成度比大规模集成电路(LSI)更高级的新型电路。大规模集成和超大规模集成的划分,目前还没有一个很确切而有科学根据的界限。一般的说法是:每个芯片上有100～5000个门或1000～10万个元件的集成电路为大规模集成,门数或元件数     

集成电路的制版

引言随着超大规模集成电路的飞速发展,制版问题越来越为人们所重视。在超大规模集成电路诸多工艺中,首先引进计算机辅助设计和计算机辅助制版,从而大大地促进了集成电路的迅速发展。大规模集成电路中,制版起着决定性的因素。在集成电路诸多专用设备中,制版的专用设备不断更新换代,其目的就是想方设法解决集成电路的制版问题。     

试论高速数字电路的设计

顺应时代的发展,高速大规模、超大规模数字集成电路不断涌现,在高速数字电路的设计中,需要对数字电路的噪讯干扰进行处理,要注意把握数字技术与模拟技术的融合,数字集成电路的选择都是应该注意的问题。     

VLSI CMOS模拟集成电路可靠性仿真设计技术

随着超大规模CMOS模拟集成电路工艺技术进入纳米阶段,模拟集成电路面临着日益严峻的可靠性挑战,可靠性仿真设计技术已经成为提升电路固有可靠性的重要途径.对现有的模拟集成电路可靠性仿真设计的文献资料进行了总结,探讨了集成电路可靠性仿真分析的高效方法,这些方法能够帮助电路设计师对电路进行分析,并找出其中的薄弱环节.介绍了典型的更具适应性和自愈能力的模拟集成电路设计技术.     

MC145156锁相环频率合成器的单片微机控制

频率合成器是通信、雷达、测量设备的一种基本部件。目前,已将锁相技术、娄字分频技术、超大规模集成电路技术结合起来,研制并生产了一系列大规模集成电路锁相环频率合成器(LSI PLL Frequencysynthesizer),集成电路芯片MC145156就是其中之一。单片微机与大规模集成电路锁相环频率合成器结合所组成的系统,具有频率稳定度高、频谱纯、频率变化范围宽、可选信道数目多、系统调试方便、可靠性高、成本低、体积小等特点。下面我们介绍MCS-51单片机与MC145156锁相环频率合成器所组成的系统,重点介绍MCS-51单片微机对MC145156的控制。     

通信LSI/VLSI工艺

本文介绍通信LSI/VLSI电路制作技术中目前比较通用的工艺。总的来说,通信电路工艺是以前LSI/VLSI22艺的继续和发展。文中论述的重点是那些和过去LSI/VLSI工艺不同的方面,而这些方面主要体现在模拟电路的制作工艺上。     

通信电路LSI／VLSI发展的新领域

本文介绍了通信技术和通信电路的发展情况,论述了通信技术和通信电路与通信LSI/VLSI发展的密切关系以及通信电路技术的特点;并通过实例说明通信LSI/VLSI中典型的电路和技术。     

Acceptable Testing of VLSI Components Which Contain Error Correctors

If a VLSI chip is partitioned into functional units (FU's) and redundant FU's are added, error correcting codes maybe employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thns obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability.     

Ultrahigh-speed HEMT LSI technology for supercomputer

The current status of high electron mobility transistor (HEMT) technology at Fujitsu for high-performance VLSI is presented, focusing on device performance in the submicrometer dimensional range and the HEMT LSIs implemented in supercomputer systems. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. A 1.1 K-gate bus-driver logic LSI has been developed to demonstrate the high-speed data transfer in a high-speed parallel processing system at room temperature, operating at 10.92 GFLOPS. A cryogenic 3.3 K-gate random number generator logic LSI with maximum clock frequency of 1.6 GHz has also been developed to demonstrate the high-clock-rate system operations at liquid-nitrogen temperature. For VLSI level complexity, a HEMT 64-kb static RAM with 1.2-ns access operation and a 45 K-gate gate array with 35-ps logic delay have been developed operating at room temperature, demonstrating the high performance required for future high-speed computer systems     

Devices and circuits for bipolar (V)LSI

It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit. General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor fT, and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes. Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design. Logic circuits (such as I²L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed.     

LSI高密度封装的类型

随着LSI和VLSI的飞速发展,LSI高密度封装技术变得越来越重要。本文叙述了高密度封装的类型,介绍了它们的一般结构,并提供了封装的外形标准。     

In-situ testability design (ISTD)—A new approach for testing high-speed LSI/VLSI logic

After a discussion of the main problems encountered in conventional methods used for testing high-speed LSI/VLSI logic, a new approach, to be called the "in-situ testability design" (ISTD), will be presented. The approach consists of extending the use of latches and serial-shift arrangements (SSA's) provided in the hardware system to be tested, by incorporating on-chip feedback arrangements designed in such a way that the chips and modules will be self-sufficient for testability-that they will be testable in-situ and in-isolation, despite their interconnections after being assembled in the system. By proper design, chips can be made testable also on-wafer prior to their dicing. For economical implementation, arrangements for sharing the use of latches and multiplexors will be introduced and explained. The ISTD approach will fundamentally simplify and facilitate the testing of high-speed LSI/VLSI logic and greatly reduce the costs of test equipment and testing. Design procedure for its implementation, and test strategy based on its use, will be described.     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

Evaluation technology of VLSI reliability using hot carrierluminescence

An evaluation technology for VLSI reliability using hot carrier luminescence has been developed. Problems with conventional electrical methods have been solved by the analysis of weak luminescence emitted from operating devices. Two applications are described. First, for the gate oxide evaluation, it is found that the best stress condition is determined by monitoring uniform photon count distribution emitted from the gate capacitors. Second, a method is proposed to find the weakest transistor in an LSI circuit against hot-carrier-induced degradation by counting photon emissions. This method is applied to the analysis of SRAMs (static RAMs) when the transistors to be improved have been detected     

0．5μm CMOS标准单元库建库流程技术研究

标准单元库是LSI/VLSI自动化设计的基础。基于0．5μm CMOS单多晶三铝工艺线,开发了全套0．5μm CMOS标准单元库。文章重点介绍了CMOS标准单元库的建库流程技术。此技术可以有效地应用于其他CMOS或SOI工艺标准单元库的开发。