On singular nonlinearH ∞ control: A state-space approach

A simple state-space approach for the four-block singular nonlinearH control problem is proposed in this paper. This approach combines a (J, J)-lossless and a class of conjugate (J, J)-expansive systems to yield a family of nonlinearH output feedback controllers. The singular nonlinearH control problem is thus transformed into a simple lossless network problem that is easy to deal with in a network-theory context.This work was supported by the National Science Council, Republic of China, under contract NSC 87-2218-E009-026.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

On the distribution of characteristics in bijective mappings

Differential cryptanalysis is a method of attacking iterated mappings based on differences known as characteristics. The probability of a given characteristic is derived from the XOR tables associated with the iterated mapping. If is a mapping : Z ₂ ^m , then for each , X, Y Z ₂ ^m the XOR table for gives the number of input pairs of difference X=X+X for which gp(X)+(X)=Y.The complexity of a differential attack depends upon two properties of the XOR tables: the density of zero entries in the table, and the size of the largest entry in the table. In this paper we present the first results on the expected values of these properties for a general class of mappings . We prove that if : Z ₂ ^m Z ₂ ^m is a bijective mapping, then the expected size of the largest entry in the XOR table for is bounded by 2m, while the fraction of the XOR table that is zero approaches e ^–1/2=0.60653. We are then able to demonstrate that there are easily constructed classes of iterated mappings for which the probability of a differential-like attack succeeding is very small.The author is presently employed by the Distributed System Technology Center, Brisbane, Australia.     

Gaussian radial basis functions and inner product spaces

An approximation result is given concerning Gaussian radial basis functions in a general inner product space. Applications are described concerning the classification of the elements of disjoint sets of signals, and also the approximation of continuous real functions defined on all of ⁿ using radial basis function (RBF) networks. More specifically, it is shown that an important large class of classification problems involving signals can be solved using a structure consisting of only a generalized RBF network followed by a quantizer. It is also shown that Gaussian radial basis functions defined on ⁿ can uniformly approximate arbitrarily well over all of ⁿ any continuous real functionalf on ⁿ that meets the condition that |f(x)|0 as x.     

Some properties of order-Statistics filters

LetX ₁,X ₂,... be a stationary sequence of random variables with Pr{X _t, x}=F(x),t=1, 2,... Also let _i ^n,(t) ,i=1,...,n, denote the ith order statistic (OS) in the moving sample (X _t–N ,...,X _t,...,X _t+N) of odd sizen=2N+1. ThenY _t=a _i X _i ^n(t) with a _i=1 is an order-statistics filter. In practicea _i0,i=1,...,n. Fort>N, the sequence {Y _t} is also stationary. IfX ₁ X ₂, ... are independent, the autocorrelation function (r)=corr(Y _t,Y _t+r) is zero forr >n – 1 and forr n – 1 can be evaluated directly in terms of the means, variances, and covariances of the OS in random samples of sizen +r fromF(x).In special cases several authors have observed that the spectral density functionf() of {Y _t} is initially decreasing for > 0. This result is made more precise and shown to hold generally under white noise. The effect of outliers (impulses) is also discussed.This research was supported by the U.S. Army Research Office.     

Explicit formulae for completions of linear time varying singular systems of differential equations

Completions of linear time varying singular systems of the formE(t)x(t)+F(t)x(t)=f(t) are explicitly computed using recent results on rational matrix functions. The algorithm and the theory behind it are carefully described. Computational issues are discussed.Research supported in part by the U.S. Army Research Office under DAAL03-89-D-0003, and the National Science Foundation under ECS-9012909.     

Geometric properties of nonlinear networks containing capacitor-only cutsets and/or inductor-only loops. Part I: Conservation laws

This paper is the first in a two part sequence which studies nonlinear networks, containing capacitor-only cutsets and/or inductor-only loops from the geometric coordinate-free point of view of differentiable manifolds. Given such a nonlinear networkN, with °₀ equal to the sum of the number of independent capacitor-only cutsets and the number of independent inductor-only loops, we establish the following: (i) circuit theoretic sufficient conditions to guarantee that the set ⁰, of equilibrium points is a ₀-dimensional submanifold of the state space ofN; (ii) circuit theoretic sufficient conditions for the condition thatN has ₀ independent conservation laws and hence that through each point of the state space ofN, there passes a codimension ₀ invariant submanifold ^* of the network dynamics; (iii) circuit theoretic sufficient conditions to guarantee that the manifolds ^* and ⁰ intersect transversely.This work was supported by the Natural Sciences and Engineering Research Council of Canada, under Grant Number A7113, and by scholarships from the Natural Sciences and Engineering Research Council of Canada and the Ontario Provincial Government.     

1D GaAs Detector Arrays for Digital X-ray Imaging with a 108-μm Spatial Resolution

A 1D x-ray detector array of pitch 108 m is designed, fabricated, and tested. The array is based on the p⁺–n–n–n⁺ structure made in epitaxial GaAs technology. Guard rings are incorporated to reduce detector cross coupling. It is announced that the technology proposed will be used to make arrays with a pitch of 50 m and a spatial resolution of 10 line-pairs/mm, suitable for digital mammography.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

Iteration and functional expansions

In a recent paper on nonlocal expansions necessary and sufficient conditions are given under whichf ^–1 has a generalized power series expansion, whenf is an invertible locally Lipschitz map between certain general subsets of a complex Banach space. Here we establish the validity of a conceptually interesting algorithm for obtaining the expansion.Basically, we show that a certain contraction mapping iteration generates iterates ₁, ₂,... such that each _k yields all of the terms of the generalized power series expansion off ^–1 up to order (k + 1), assuming merely that the expansion off ^–1 exists. An earlier different result along related lines is mentioned.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

WDM Intelligent Transport Network for All-Optical Routing

Conventional optical wavelength division multiplexing (WDM) networks calls for optoelectronic conversion for each wavelength in every node plus a large management effort for proper packet routing. All-optical networks are still unavailable. Here, a new architecture is described where the optical transport is done without conversions (except at extreme nodes), and with minimal routing management effort. The present basic mechanism is, firstly, to gather (at any source node) the packets demanding for a certain destination node K. Secondly, all these packets are modulated onto wavelength K. Next, the wavelength is routed towards node K by passive directional devices. As other source nodes reuse wavelength K, an anti-collision mechanism is presented. This mechanism uses very economic and widely available components. The present arrangement seems to be pre-wired, conveying packets from source to destination nodes almost automatically. The present arrangement is simpler and far more economical than (G)MPL()S arrangements, for instance. Additionally, the present system does not demand for expensive wavelength conversions or central protocols. The disadvantage over (G)MPL()S is that the present arrangement limits its maximum number of operational nodes to the number of wavelenghts WDM is able to support.     

Pervasive Home Environments

For decades, technologists have been promising the intelligent house. The vision is usually portrayed as a house filled with technology which will do the dweller's bidding and take all domestic drudgery out of their lives. The truly intelligent house is still some way off, but the emergence of broadband, availability of faster, smaller and ever cheaper computing equipment and a variety of wired and wireless network technologies are enabling technologies that bring this vision closer to reality. These technology trends lead to the concept that computing and other smart devices will become pervasive, fully networked and disappear into the infrastructure of the home. People will carry out their tasks unaware of the complexity of the infrastructure that supports their activities in much the same way as people today use mains electricity.This paper introduces these concepts and discusses the technological challenges to be overcome. We present our vision of the pervasive home environment where inhabitants can focus on tasks rather than the technology: I need to create X and send it to Y rather than I need to use this computer and this application which needs access to service A and resource B. Although this sounds simple, the environment needs to understand who I is, and who or what Y is. Appropriate permissions must be in place and resources allocated, if available. The most appropriate interface for the task and user must be determined.The pervasive, intelligent home will make available new ways to access and share information. It will herald new services, such as care and support of people in the home, entertainment, educational and security services. The final part of the paper discusses the commercial opportunities and challenges which must be met, not least the need for industry to agree on open standards and interfaces.     

One canonical form for higher-index linear time-varying singular systems

One form of the singular systemAx+Bx=f is considered. The analytic solution, perturbation, and numerical solution of this form are examined. A class of systems which may be transformed into this form without altering these properties is characterized.Research sponsored by Air Force Office of Scientific Research, Air Force Systems Command, under Grant No. AFOSR-81-0052A. The United States Government is authorized to reproduce and distribute reprints for governmental purposes not with-standing any copyright notation here on.     

An Analog Self-Test Based on Differential I DD Monitoring Supported by Differential I OUT Checking

This paper proposes a novel DFT scheme that combines two test techniques—differential power supply current (I _DD ) monitoring and differential output current (I _OUT ) checking—in a single analog self-test. The DFT scheme is aimed at fully differential analog circuits. Fault detection is provided by means of differential measurement of the on-chip parameters, such as the I _DD and I _OUT currents. Due to the differential nature of the test principle used, no reference measurement is required prior to the test, thus the fault detection exhibits a significantly reduced dependency on process parameter variations, variation of temperature during the test as well as outside interference's. Based on measurement results, the realistic tolerance band for fault detection was determined and the fault coverage, resulting from previous simulation experiments, was adjusted.     

Power Consumption of Quasi-adiabatic Logic Gates

A computer simulation is carried out to investigate the power consumption of major quasi-adiabatic logic gates. Anomalously high dissipation is found at low clock rates. An explanation for the anomaly and a method of eliminating this are proposed. For the dissipated energy W and the clock rate f, it is found that W f C ^{1 +} as f tends to infinity, where is essentially less than unity. The mechanism of the phenomenon is identified. Rules are established that govern the power consumption of the logic gates. It is concluded that they should help one to strike a balance between power consumption and speed, to optimize power characteristics, and to predict the performance of future models made by better process technologies.     

A VLSI decoder for a new type of constellations adapted to the Rayleigh Fading Channel

Diversity is the key solution to obtain efficient channel coding in wireless communications, where the signal is subject to fading (Rayleigh Fading Channel). For high spectral efficiency, the best solutions used nowadays are based on QAM constellations of 1-order diversity, associated with a binary code or a trellis coded modulation to increase the overall diversity. It has been shown that a new class of d-dimensional non-QAM constellations, named -constellations, can bring a d-order diversity without the addition of redundancy. Combined with classical coding techniques, -constellations are very efficient. However, the decoding algorithm is far more complicated for -constellations than for QAM-constellations. A sub-optimal algorithm that allows the decoding of -constellations is proposed. An example of an application for a 4 bits/Hz/s spectral efficiency with a 4-D -constellation is given. The VLSI architecture of the decoder is described. The implementation leads to 72 K gates, a binary rate of 32 Mbits/s and a BER of 10^-3 for a SNR of 14 dB.     

Parametric toeplitz systems

This paper investigates the properties of the two-variable polynomialu (, z) built on the first column of the adjoint matrix ofI -C, whereC is a given Hermitian Toeplitz matrix. In particular, the stability properties ofu (,z) are discussed and are shown to depend essentially on the location of X with respect to the eigenvalues ofC. The eigenvectors ofC, which have recently found some applications in signal processing and estimation theory, are obtained from the polynomialu(,z) when tends to the eigenvalues ofC. This allows one to derive several results concerning the eigenpolynomials, including those for the case of multiple eigenvalues.     

On the structure of the privacy hierarchy

An N argument function f(x ₁,...,x _N ) is called t-private if a protocol for computing f exists so that no coalition of at most t parties can infer any additional information from the execution, other than the value of the function. The motivation of this work is to understand what levels of privacy are attainable. So far, only two levels of privacy are known for N argument functions which are defined over finite domains: functions that are N-private and functions that are (N – 1)/2-private but not N/2-private.In this work we show that the privacy hierarchy for N-argument functions which are defined over finite domains, has exactly (N + 1)/2 levels. We prove this by constructing, for any N/2 t N – 2, an N-argument function which is t-private but not (t + 1)-private.This research was supported by US-Israel Binational Science Foundation Grant 88-00282.     

Fault diagnosis in reconfigurable VLSI and WSI processor arrays

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The divide and conquer technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(V^1/2) for the processor arrays considered in this paper, where V is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.