An equivalent‐circuit modelling on vertical and horizontal integrations for MOS flat‐band voltage simulation

The fixed oxide charge will cause the MOS capacitor (MOS‐C) flat‐band voltage to shift. We can observe the potential distribution to determine the MOS‐C flat‐band voltage. However, the potential distribution can be obtained from the integration of the electric field distribution. The integration of the electric field distribution is classified into the vertical and horizontal integrations. In this paper, we use the equivalent‐circuit model to demonstrate the flat‐band voltage of the non‐ideal MOS‐C. The equivalent‐circuit model of Poisson's equation includes two fixed charges Q′_f1 and Q′_f2 in the oxide layer region. Because the horizontal integration method is the superposition method, the equivalent‐circuit model for the horizontal integration is divided into 3 types. Hence, the flat‐band voltage for the horizontal integration is equal to the sum of the V_G1, V_G2, and V_G3 for the flat‐band condition. By comparison, the simulation results of the horizontal integration method approximate to the vertical integration method. Copyright © 2006 John Wiley & Sons, Ltd.     

Characteristics of N2/SF6 mixture gas in creeping discharge developing in narrow gap with backside electrode

The flashover voltage with a backside electrode was found to be lower than that without the backside electrode. Under microsecond pulse voltage application, we describe the characteristics of a creeping discharge developed in the narrow gap with the backside electrode. Using a CCD camera and ultrahigh‐speed camera, we observed the corona extension processes. The lowest flashover voltage was found to be obtained at positive polarity with a SF₆ content D = 3%. In the corona extension obtained using an ultrahigh‐speed camera, peculiar differences were observed in the corona extension process. The corona extension increased, and rapid flashover was observed at D = 3%. Using a CCD camera, small coronas were detected from the backside electrode. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 158(2): 31–38, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20431     

Simulation of slow current transients and current collapse in GaN FETs

Two-dimensional transient simulations of GaN MESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V _D is raised abruptly (while keeping the gate voltage V _G constant), the drain current I _D overshoots the steady-state value, and when V _D is lowered abruptly, I _D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes. We also calculate a case when both V _D and V _G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V _D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.     

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

A wave‐front‐time dependent corona model for transmission‐line surge calculations

For transmission‐line surge studies, the inclusion of corona discharge due to high voltage surges is important as well as the inclusion of frequency‐dependent effects. Because the charge‐voltage (q‐v) curve of a lightning surge is different from that of a switching surge, a corona model should reproduce different q‐v curves for different wave‐front times. The present paper proposes a wave‐front time dependent corona model which can express the dependence by a simple calculation procedure as accurately as a rigorous finite‐difference method which requires an enormous calculation time. The simplicity enhances the incorporation of the corona model into a line model, because a large number of models are to be inserted into the line model by discretization. The q‐v curves calculated by the proposed method agrees well with field tests. This paper also proposes an efficient method to deal with nonlinear corona branches in distributed‐parameter line model using the trapezoidal rule of integration and the predictor‐corrector method. © 1999 Scripta Technica, Electr Eng Jpn, 129(1): 29–38, 1999     

Deterioration of device characteristics of MFSFET due to fatigue

Abstract

Change of device characteristics of the metal-ferroelectric-semiconductor FET (MFSFET) with the progress of fatigue of the ferroelectric thin film are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V_G curves exhibit the accumulation, the depletion and inversion regions clearly. They also exhibit the memory window of 2V. I_D-V_D curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I_D-V_D curve is 6mA/cm², which decreases as much as 50% after fatigue. Our model is expected to be very useful in the estimation of the behaviour of MFSFET devices with the progress of fatigue.     

A gain/efficiency‐enhanced bidirectional switched‐capacitor DC‐DC converter

A closed‐loop gain/efficiency‐enhanced bidirectional switched‐capacitor converter (BSCC) is proposed by combining an adaptive‐conversion‐ratio (ACR) phase generator and pulse‐width‐modulation (PWM) controller for bidirectional step‐up/down DC‐DC conversion and regulation. For realizing gain‐enhanced, the power part consists of one m_c‐stage cell and one n_c‐stage cell in cascade between low‐voltage (LV) and high‐voltage (HV) sides to boost HV voltage into m_c × n_c times voltage of LV source at most, or convert LV voltage into 1/(m_c × n_c) times voltage of HV source at most. For realizing efficiency‐enhanced, the ACR idea with adapting stage number m, n is built in the phase generator to obtain a suitable step‐up/down gain: m × n or 1/(m × n) (m = 1, 2, …, m_c, n = 1, 2, …, n_c). Further, the output regulation and robustness to source/loading variation can be enhanced by PWM on the LV/HV sides. Some theoretical analysis and control design are included as: modeling, steady‐state analysis, conversion ratio, efficiency, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a BSCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Quantitative evaluation of lightning surge range voltage–time characteristics in high‐pressure SF6 gas

Gas‐insulated switchgear (GIS) is subjected to very fast transient overvoltages such as lightning surges or disconnector switching surges. Therefore, the sparkover voltage and time (V?t) characteristics of SF₆ in a very short time range of less than are of great interest from the viewpoint of insulation design and coordination for a GIS. This paper describes the V?t characteristics of SF₆ at a gas pressure of 0.5 MPa using a steep‐front square impulse voltage under a quasi‐uniform field gap and presents a quantitative evaluation of the V?t characteristics for a nonstandard lightning impulse voltage. In the case of a square impulse, the V?t characteristics of positive polarity were observed to be almost flat over a long time range from 80 ns to , and rose steeply over a short time range from 80 ns down to 20 ns. For negative polarity, the V?t characteristics exhibit a gentle rise from 200 ns down to 40 ns. In the estimation of V?t characteristics, the equal‐area criterion parameters were quantitatively estimated using the square impulse. For a nonstandard lighting impulse, we found that application of the equal‐area criterion with these parameters for the nonoscillating impulse and oscillating impulse of up to 5.3 MHz as a model of lightning surge and disconnector switching surge is possible. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 159(4): 8– 17, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20309     

Proposal of flux‐lock‐type fault current limiter with high‐TC superconducting element

This paper proposes a new type of fault current limiter (FCL), which consists of a high‐T_C superconducting (HTS) element and two coils wound on the same core without any leakage magnetic flux. In this FCL, either the limiting impedance or the initial limiting current level can be controlled by adjusting the inductances and the winding direction of the coils. Therefore, this FCL could relax the material restrictions on high‐T_C superconducting FCL. A current‐limiting experiment by a model FCL was carried out, and the limiting performance was observed. The initial limiting current level of the model FCL was 1.7 times higher than the critical current of the HTS element, and the fault current is suppressed to 52% immediately after the short‐circuit in the test. Considering voltage–current characteristics of a high‐T_C superconductor in a computer simulation, the calculated results almost agreed with the experimental results. © 1999 Scripta Technica, Electr Eng Jpn, 127(1): 31–38, 1999     

Effects of Long-Time DC Bias on D2O- and D2/N2-Annealed BST Thin Films

Effects of long time dc bias on both D₂O- and D₂-annealed BST thin films were investigated by secondary ion mass spectrometry (SIMS) analysis and electrical measurements before and after bias stressing. Bias conditions were sufficient to cause the degradation of (1) subsequently-measured current density-voltage characteristics and (2) a significant positive shift of the capacitance-voltage curve along the voltage axis. This latter effect may be attributed to the asymmetric space charge distribution in the BST thin film after bias stressing or, possibly, to changes in the interface state density. No significant deuterium motion was observed in D₂O-annealed capacitors biased at an elevated temperature or in D₂/N₂-annealed capacitors biased at room temperature in high electric fields (3.5 × 10⁷ V/m) for more than 8 hours. The small values of the D_i mobility which were inferred from the SIMS results are consistent with recent data on the kinetics of deuterium incorporation in and removal from similar BST thin films.     

带开关电容网络的交错并联磁集成电感Boost变换器

针对传统交错并联Boost变换器电压增益低、开关管电压应力高、电感电流纹波大等问题,提出一种新型交错并联Boost变换器。该变换器用2个开关电感单元分别代替储能电感L₁和L₂,并对开关电感进行耦合集成,在此基础上增加了1个二极管和2个电容构成开关电容网络。分析了变换器在不同占空比下的工作模态,推导了电压增益公式,分析了开关管电压应力和电感电流纹波的大小。与传统交错并联Boost变换器相比,该变换器性能得到明显提升,尤其在占空比D>0.5的情况下电压增益是传统交错并联Boost变换器的3（1+D）倍,开关管的电压应力减小了2/3,电感电流纹波也减小近一半。最后实验验证了理论分析的正确性。表明带开关电容网络的交错并联磁集成电感Boost变换器有着优良的工作性能。     

磁集成开关电感高增益级联Boost变换器

提出一种改进型具有开关电感单元的磁集成高增益级联Boost变换器,该级联变换器采用开关电感单元代替传统级联Boost变换器的储能电感并将电感进行耦合集成。改进后的变换器较传统Boost变换器的电压增益提高(1+D)~2/(1-D)倍,较传统级联Boost变换器的电压增益提高(1+D)~2倍,且电感电流纹波减小到其15%以下。通过分析变换器工作原理、推导出电压增益及等效电感的表达式,设计出耦合电感的集成方案,并利用仿真和实验验证了集成方案的正确性,可充分表明改进型级联Boost变换器具有更佳的工作性能。     

Insulation characteristics of GIS under nonstandard lightning‐impulse oscillations: Insulation characteristics under single‐frequency oscillations with various frequencies and damping ratios

To improve GIS insulation specifications, it is important to recognize the insulation characteristics under oscillatory overvoltage waveforms occurring in the field. This paper describes investigations of insulation characteristics for single‐frequency oscillatory waveforms with various frequencies and damping ratios. It was found that minimum breakdown voltages (V_min) rose with frequency rising under the same damping condition and V_min rose with damping ratio rising under the same frequency condition. From an analysis of actual breakdown voltage characteristics, the probability of breakdown at a valley of oscillation rose with damping increasing. It was found that the insulation characteristics were treated all‐inclusively based on the characteristics of V_min for rise time or damping time. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(3): 43–49, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10156     

Measurement of dynamic magnetic loss parameter in ferrites

The measurement of the iron loss in ferrites is important for developing high‐efficiency switching power supplies. The authors have proposed the dynamic magnetic loss parameter, λ_f, for evaluating the iron loss in ferrites. In previous studies, the parameter was assumed to be a constant value for an individual ferrite material and defined for one period of a small B–H loop. In this paper, assuming that λ_f is a function of the time derivative of the magnetic flux density, dB/dt, a novel measurement method of λ_f of a Ni‐Zn ferrite is proposed using rectangular wave voltage excitation and the Fourier expansion of the exciting current. In order to realize an iron loss measurement system with the rectangular wave voltage excitation, a high‐frequency FET inverter has been developed. The results of measuring λ_f show that it is uniquely determined by dB/dt regardless of the B–H loop size. The measured dB/dt characteristics of λ_f are applied to practical examples for switching power supplies and sinusoidal wave voltage excitations. Their experimental and computational results coincide and it is clarified that the measured dB/dt characteristics are effective and useful. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 156(1): 1–6, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20101     

PD time‐sequential properties of SF6 and SF6 gas mixture including CO2

This paper deals with partial discharge (PD) time‐sequential properties of SF₆/N₂/CO₂ ternary gas mixture as well as SF₆ and SF₆/N₂ gas mixture under AC and positive DC voltage applications. The measurements were carried out by changing the gas pressure up to 0.6 MPa and applied voltage with the N‐shape characteristics of breakdown voltage versus gas pressure for each tested gas considered. We obtained experimental results of the gas pressure dependence of maximum peak value of PD current pulse as well as the relationship between the time interval of PD pulses and the peak value of PD pulse. We discuss the mechanism of increase in breakdown voltage by adding CO₂ into SF₆/N₂ gas mixtures in terms of change of PD type from streamer to leader discharge. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 151(3): 32–40, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20073     

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

Nonlinear DC equivalent circuits for ferroelectric memristor and Its FSM application

Pt/BaTiO₃-BiFeO₃/Nb:SrTiO₃ based memristors were fabricated and their current–voltage (I–V) characteristics were studied in order to facilitate integration with analog/digital computations. Piecewise non-linear I–V characteristic equations of the ferroelectric memristor were obtained using non-linear regression techniques. An equivalent circuit for the fabricated memristors was obtained comprising of internal current, film resistance, and voltage dependent resistance. Utilizing the equivalent circuit model, a three bit general purpose Finite State Machine was developed and simulated results were found to match with the fabricated FSM device results.     

磁集成高增益Zeta变换器研究

针对传统升压变换器升压能力不足的问题,提出一种改进型磁集成高增益Zeta变换器。分析了该变换器的工作原理以及工作模态,推导了输出电压增益公式,分析了二极管、开关管、电容的电压应力,引入磁集成技术对电感进行耦合,减小了变换器体积和电感电流纹波。与传统Zeta变换器相比,电压增益提高了（3D+1）/D倍,电感电流纹波减小1/2。通过PSIM仿真软件对理论分析进行仿真验证,并制作实验样机对仿真和理论分析进行了验证。     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Synthesis of superconducting Bi2Sr2CaCu2O8+δ single crystals using alumina crucibles with different purities

A self‐flux method is the simplest technique for synthesizing Bi₂Sr₂CaCu₂O_8+δ (Bi‐2212) superconducting single crystals. However, the crystals are inevitably contaminated because of the Bi‐2212 stoichiometric melt reacting with the crucible material. In this paper, we investigate the nonsuperconducting subproduct that forms during heating in the self‐flux method for synthesizing Bi‐2212. This subproduct was identified as BiSr₂CaAl₃O₉ by X‐ray diffraction. Bi‐2212 crystal growth was performed using A1₂O₃ crucibles with three different purities (nominally 97, 99.7, and 99.9%). For both the 97 and 99.7% purity crucibles, the subproduct was observed in all five samples out of five, whereas for the 99.9% purity crucible, it was observed in only two samples out of five. Furthermore, the 99.9% purity crucible gave a much lower subproduct volume than the 97% purity crucible. The average superconducting critical temperature (T_c,zero) varied depending on the crucible purity; it was 89.6, 90.8, and 91.8 K for the 97, 99.7, and 99.9% purity crucibles, respectively. Finally, we fabricated Bi‐2212 stacked devices with intrinsic Josephson junctions (Bi‐2212 stack) using as‐grown crystals from the 97 and 99.9% purity crucibles. The Bi‐2212 stacks exhibited a highly hysteretic current–voltage characteristic even at liquid N₂ temperature and they had identical quality parameters for Josephson junctions (i.e., I_r/I_c and voltage jump V_j). We conclude that the subproduct formation has little effect on the electrical characteristics of a Josephson junction device at 77 K. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.