IGBT模块驱动及保护技术

对IGBT的栅极驱动特性、栅极串联电阻及IGBT的驱动电路进行了探讨。给出了过电流保护及换相过电压吸收的有效方法。     

基于有源电力滤波器的IGBT驱动及保护研究

介绍了采用M57962L设计的有源滤波器中绝缘栅场效应晶体管（IGBT）驱动器的驱动原理和电路特点,对IG—BT的栅极驱动特性、栅极串联电阻进行了探讨,给出过流保护和过压吸收的有效方法。样机试验证明了此种设计方案可靠、有效。     

一种IGBT全桥逆变驱动电路的设计

简单阐述了2SC0435T模块的特点和IGBT的H桥互锁电路的特点。以2SC0435T为核心,给出了直接模式下的外围电路,以驱动IGBT全桥逆变电路。设计了栅极电阻的接法及其阻值的大小以及IGBT的栅极过压保护电路,给出了驱动信号波形,同时验证了此驱动器具有良好的保护功能和驱动功能。     

在线研讨会——与最新的产品发展、解决方案和技术更新同步

利用智能栅极驱动光耦解决设计难题时间:2012-12-6绝缘栅极晶体管(IGBT)及其功率模块一直是太阳能逆变器、马达驱动和不间断电源(UPS)等大功率工业应用的首选开关器件,因而需要栅极驱动电路来提供优化驱动和保护功能。最近飞兆半导体开发出一款具有优化成本、高可靠性的IGBT驱动光耦产品     

基于M57962L的IGBT驱动电路

IGBT具有开关速度快、栅极驱动电流小、驱动功率大等特点得到广泛应用。针对IGBT驱动的实际要求,介绍了IGBT工作特性,并利用M57962L设计出一种适用的IGBT驱动电路。     

压接型IGBT内部栅极电压一致性影响因素及调控方法

压接型绝缘栅双极晶体管(IGBT)的驱动印制电路板(PCB)寄生参数不一致会引起瞬态过程中内部IGBT芯片栅极电压不一致,芯片不能同时开通,造成芯片的瞬态不均流.结合压接型IGBT驱动PCB结构及运行工况,建立了包含驱动源、芯片模型、驱动PCB的一体化电路模型,分析了栅极内电阻、栅射极电容以及驱动电阻对驱动电压一致性的影响.在此基础上提出了驱动PCB电感匹配、并联芯片数匹配以及集中电阻补偿的驱动PCB的调控方法,以实现对栅极电压一致性的有效调控.研究表明驱动电阻是造成芯片栅极电压不一致的主要因素.利用上述调控方法可将芯片开通时间的不均衡度由79.2％分别降低至2.86％、7.1％和7.5％,实验验证了所提出的驱动PCB调控方法的有效性.     

绝缘栅双极晶体管（IGBT）模块驱动及保护

对IGBT栅极驱动特性、栅极串联电阻及其驱动电路进行了探讨，提出了慢降栅压过流保护和过电压吸收的方法。     

IGBT调制器工作状态及其栅极驱动特性分析( 上)

叙述了固态调制器过压和欠压状态的特点,伏安特性曲线和负载线在工程设计中的重要性.介绍了160个IGBT开关管组成的串联开关调制器工作状态选择,不同的工作状态对驱动电路设计提出了不同的要求和为了满足技术要求,在电路上必须采取的技术措施.给出的IGBT栅极驱动特性、密勒效应的数学表达式及其对栅极电压UGE波形的影响,为后面将要介绍的部分设计分析奠定了专业理论基础.     

一种用于光隔离IGBT栅极驱动的智能型LED驱动电路

采用双极型工艺设计了一种智能型高速LED驱动电路,可用于光隔离IGBT栅极驱动芯片的输入驱动。该设计采用一种新型逻辑门结构来实现信号传输、故障反馈以及外部置位等功能,同时达到降低信号传输延迟时间的目的。测试结果表明,在常温条件下,LED驱动电路的输入信号传输延迟时间为70 ns,复位信号有效到故障消除的延迟时间为4.59μs。所设计的驱动电路能够满足光耦隔离IGBT栅极驱动芯片的使用要求。     

影响IGBT驱动电路性能参数的因素分析

分析了桥式电路中IGBT的动态开关过程以及IGBT的栅极、发射极和集电极的分布电感与其他分布参数的综合作用对IGBT驱动电路的影响,并且通过实验验证了理论分析的正确性,最后指出了IGBT驱动电路设计时的注意事项。     

基于光耦HCPL316J的大功率IGBT驱动电路研究

本文主要对逆变器等功率装置的IGBT驱动电路进行研究,从门极驱动电压、门极驱动电阻、驱动电路功率与IGBT的关系以及驱动保护等方面分析了驱动电路的设计。最后设计了以基于光电耦合器HCPL316J的驱动电路,计算了电路的参数。通过驱动实验和短路保护实验,验证了设计的正确性。     

新型集成隔离光耦模块原理及驱动设计

针对IGBT驱动电路的特点,本文分析了一种新型智能集成光电隔离驱动器ACPL332J的工作原理,并详细介绍了其保护控制逻辑和驱动设计中所注意的一些问题。相比较其他传统的隔离光耦驱动模块而言,ACPL332J具有独特的有源米勒箝位特性。实验结果验证了原理分析的有效性,该设计电路已经在实际系统中得到应用。     

A resonant MOSFET gate driver with efficient energy recovery

High frequency pulse-width modulation (PWM) converters generally suffer from excessive gate drive loss. This paper presents a resonant gate drive circuit that features efficient energy recovery at both charging and discharging transitions. Following a brief introduction of metal oxide semiconductor field effect transistor (MOSFET) gate drive loss, this paper discusses the gate drive requirements for high frequency PWM applications and common shortcomings of existing resonant gate drive techniques. To overcome the apparent disparity, a new resonant MOSFET gate drive circuit is then presented. The new circuit produces low gate drive loss, fast switching speed, clamped gate voltages, immunity to false trigger and has no limitation on the duty cycle. Experimental results further verify its functionality.     

Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

Current drive enhancement by using high-permittivity gate insulatorin SOI MOSFET's and its limitation

Speed enhancement effects by using a high-permittivity gate insulator in SOI MOSFETs and its limitation were investigated by a two-dimensional device simulator and circuit simulator. The SOI structure is suitable to have excellent current drive by using a high-permittivity gate insulator. Although the gate capacitance increases as a function of its dielectric constant, the current drive does not increase proportionally due to the inversion capacitance. According to the simulation results of the delay time, when the pulse waveforms driven by a CMOS inverter are propagated through 1 mm-long interconnects, the delay time significantly reduces at a dielectric constant value of around 25 (Ta₂O₅). Thus, it is worthwhile using Ta₂O₅ for gate insulator to achieve high-speed operation. Furthermore, the reduction of source parasitic series resistance is a key issue to realize the highest current drive by using a high-permittivity gate insulator in SOI MOSFET     

A new gate drive circuit for high-speed operation of GTO thyristors

This paper presents a new gate turn-off drive circuit for GTO thyristors, which can accomplish faster turn-off switching for high-speed operation of the GTO. The switching characteristics of GTO's can be improved by use of the gate drive circuit that is able to make a very high rate of the negative gate current. The major disadvantage of the conventional gate turn-off driving technique is that it has a difficulty in realizing higher negative di_G/dt due to the maximum reverse gate-cathode voltage and the stray inductances within the gate turn-off drive circuit. This paper shows that this problem can be overcome by adding another gate turn-off drive circuit to the conventional gate turn-off drive circuit. Simulation and experimental results in conjunction with chopper circuit verify the performance of the proposed gate drive circuit     

Design of LIGBT protection circuit for smart power integration

Development of a monolithic power integrated circuit by making the lateral insulated gate bipolar transistor (IGBT) the main switching device is a current topic. The overcurrent protection scheme is usually necessary to be built as part of the function in such a power integrated circuit. The protection circuit requires distinguishing various fault conditions and reacting differently based on the device safe operating area (SOA) limitation. At the same time, the protection circuit should also be relatively concise and suitable for integration. In this paper, a concise circuit suitable for integration and with gate drive capability is proposed to provide the complete function of overcurrent SOA protection for the LIGBT. The operational principle was described in detail and the circuit performance was verified with experimental results from both the discrete circuit and the fabricated LIGBT integrated circuit     

Effect of Gate-Drive Circuits on GTO Thyristor Characteristics

This paper deals with the effects of gate drive circuits on turn-on and turn-off characteristics of GTO thyristors. The turn-on methods are outlined and their effects on switching performance are discussed. The turn-off characteristics and the failure modes associated with the storage, fall, tailing, and avalanche periods are presented. Solutions to failure modes are outlined. Both direct and indirect gate drive circuits are presented. The effects of ideal voltage source and series insertion of gate inductance to storage, fall, tailing, and avalanche breakdown period of the GTO thyristors are studied and compared. The suitability of using certain types of gate drive circuits for certain GTO thyristors is discussed.     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

基于CPLD的直流无刷电机驱动电路设计

介绍一种基于CPLD(复杂可编程逻辑器件)的直流无刷电机驱动电路,给出驱动电路的软硬件设计用软件代替逻辑门实现电机的保护逻辑。采用EPM7064SLC-44-10 CPLD为核心控制器,实现电机驱动所需的换相译码、死区发生器和IPM(智能功率模块)接口电路。系统软件采用VHDL语言编程,代替原来的RC电路实现的死区时间发生器。该电路具有体积小、调试方便、死区时间设置灵活等优点。