Sulfide treated GaAs MISFET's with gate insulator of photo-CVDgrown P3N5 film

Sulfide passivated GaAs MISFET's with the gate insulator of photo-CVD grown P₃N₅ films have been successfully fabricated. The device shows the drain current instability less than 22% for the period of 1.0 s ~1.0×10⁴ s, due to excellent properties of sulfide treated P₃N₅/GaAs interface. The effective electron mobility and extrinsic transconductance of the device are about 1300 cm²/V·sec and 1.33 mS, respectively, at room temperature. To estimate the effects of sulfide treatment on P₃N₅/GaAs interfacial properties, GaAs-MIS diodes are also fabricated     

InP MISFET's with Al2O3/Native Oxide double-layer gate insulators

Enhancement-mode InP MISFET's with anodic Al2O3/ native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500-3000 cm²/V . s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements. InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.     

InP MISFET's with plasma anodic Al2O3and interlayed native Oxide gate insulators

InP MISFET's, with native oxide film interlayed between plasma anodic Al2O3film and the InP substrate, has been fabricated and showed the instability of the drain current reduced less than ± 4 percent for the period of 5 µs ∼ 5 × 10⁴s. The effective electron mobility is 2100 ∼ 2600 cm²/V.s at room temperature. The CV characteristics of MIS diodes and AES in-depth profiles are also discussed with respect to effects of interlaying native oxide film on device characteristics.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

Gigahertz logic gates based on InP-MISFET's with minimal drain current drift

Three-input AND/NOR logic gates based on 3-µm overlapping gate InP-MISFET technology were fabricated and clocked at 1 GHz. The logic gates showed a propagation delay of ∼500-700 pS/gate for a channel length of 1.5 µm. Such high-speed performance was obtainable as a result of a novel process that was used in the fabrication of the MISFET's. The process included the saturation of InP surface with phosphorus vapor and growth of a P2OxN1-xinterfacial layer followed by the deposition of an SiO2gate insulator. MISFET's that were utilized in the logic gates showed a channel mobility of ∼3700 cm²/V.s and less than 3-percent drain current drift.     

GaInAs n-channel inversion-mode MISFET's with improved long- and short-term stability

CVD SiO2has been used as gate insulator for GaInAs n-channel inversion-mode MISFET's. By applying a rapid thermal annealing cycle with a maximum temperature of 700°C, the number of fast interface states could be strongly reduced, thus leading to stable device performance in the time range between 10^-6and 10 s. The drain current drift for longer times, however, is not affected by the annealing step. A reduction of the dielectric deposition temperature down to 250°C, however, results in improved long-term stability with a drain current decrease of only 5 percent after 10⁴s of operation at room temperature.     

InxAl1-xAs/InP heterojunction insulated gate field effect transistors (HIGFET's)

Stability problems in conventional InP metal-insulator-semiconductor field effect transistors (MISFET's) have been overcome in InP heterojunction insulated gate FET's (HIGFET's) by replacing the insulator with InxAl1-xAs. We report on the fabrication and low-frequency operation of the HIGFET with a composition of x = 0.43. Transistor characteristics have been successfully modeled by an analytical MISFET model which indicate a low interfacial state density (≅ 10¹¹/cm²) and near flat-band condition.     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

Ge3N4-InP MIS structures

MIS structures were fabricated by the low temperature pyrolytic deposition of Ge3N4on n-InP. The interface characteristics of the devices were found to depend on Ge3N4deposition parameters. For optimum deposition conditions, C-V and G-V measurements suggest the presence of an average interface state density of (2-4-) × 10¹¹cm^-2ev^-1with a time constant of 8 µs. No major hysteresis was observed in the C-V plot and the data indicates some inversion charge build-up under the application of large negative bias which could be useful for the fabrication of inversion mode MISFET's.     

Large enhancement of interband tunneling current densities of over105 A/cm2 inIn0.53Ga0.47As-based surface tunnel transistors

In_0.53Ga_0.47As-based Surface Tunnel Transistors (STT's), which control an interband tunneling current between an n-type channel and a p-type drain by an insulated gate, are investigated with the goal of increasing the tunneling current-density for high-speed operation. The fabricated devices enhanced an interband tunneling current density by a factor of 10² compared to the conventional GaAs-STT's due to a smaller bandgap energy and a lighter electron effective mass, and exhibited a clear gate-controlled negative differential resistance (NDR) characteristics with maximum tunneling current densities of over 10⁵ A/cm². The cutoff frequency (F_T) and maximum oscillation frequency (f_max ) of a fabricated device with a 1.0-μm gate length were estimated to be 7.9 GHz and 20 GHz, respectively, in the NDR region     

Self-aligned GaAs MISFET's with a low-temperature-grown GaAs gateinsulator

GaAs MISFET's with a low-temperature-grown (LTG) GaAs gate insulator and ion-implanted self-aligned source and drain n⁺ regions are demonstrated. The resistivity and breakdown field of the LTG GaAs insulator were not changed appreciably by implantation and 800°C activation annealing. The gate leakage current remained very low at a value of approximately 1 μA per μm² of gate area at 3 V forward gate bias. Because of the reduced source and drain resistance, the drain saturation current and the transconductance of self-aligned MISFET's increased more than twofold after ion implantation     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 10¹²eV^-1. cm^-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

Back-gated buried oxide MOSFETs in a high-voltage bipolartechnology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2×10¹²/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4×10¹⁰/cm² in the buried oxide     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

Effects of trap-state density reduction by plasma hydrogenation inlow-temperature polysilicon TFT

The reduction of trap-state densities by plasma hydrogenation in n-channel polysilicon thin-film transistors (poly-TFTs) fabricated using a maximum temperature of 600°C has been studied. Hydrogenated devices have a mobility of ~40 cm²/V×5, a threshold voltage of ~2 V, an inverse subthreshold of ~ 0.55 V/decade, and a maximum on/off current ratio of 5×10⁸. The effective channel length decreases by ~0.85 μm after a short hydrogenation which may be attributed to the activation of donors at trap states near the source/drain junctions. Trap-state densities decrease from 1.6×10¹² to 3.5×10¹¹ cm^-2 after hydrogenation, concomitant with the reduction of threshold voltage. Using the gate lengths at which the trap-state densities deviate from the long-channel values as markets for the leading edge of passivation, the apparent hydrogen diffusivity is found to be 1.2×10^-11 cm²/s at 350°C in the TFT structure     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm     

Ion-implanted high microwave power indium phosphide transistors

Encapsulated rapid thermal annealing (RTA) has been used in the fabrication of indium phosphide (InP) power metal-insulator-semiconductor field-effect transistors (MISFETs) with ion-implanted source, drain, and active channel regions. The MISFETs had a gate length of 1.4 μm. Six to ten gate fingers per device, with individual gate finger widths of 100 or 125 μm, were used to make MISFETs with total gate widths of 0.75, 0.8, or 1 mm. The source and drain contact regions and the channel region of the MISFETs were fabricated using silicon implants in semi-insulating InP at energies from 60 to 360 keV with doses from 1×10¹² to 5.6×10¹⁴ cm^-2. The implants were activated using RTA at 700°C for 30 s in N₂ or H₂ ambients using a silicon nitride encapsulant. The high-power, high-efficiency MISFETs were characterized at 9.7 GHz, and the output microwave power density for the RTA conditions used was as high as 2.4 W/mm. For a 1-W input at 9.7 GHz gains up to 3.7 dB were observed, with an associated power-added efficiency of 29%. The output power density was 70% greater than that reported for GaAs MESFETs