Transient Capability of Superconducting Devices on Electric Power Systems

Superconducting devices operating within a power system are expected to go through transient overload conditions during which the superconducting coil has to carry currents above the rated values. Designing the coil to remain superconducting through any possible fault scenario can be cost prohibitive, necessitating operation beyond the critical current for short periods. In order to set operating limits and design adequate protection systems for superconducting devices connected to a power system, the region of safe operation of these devices has to be described with general capability curves. Existing standards that define limits for these over-current situations are based on copper winding experience that do not apply to devices with superconducting components because of the highly nonlinear interaction between magnetic fields, operating temperature, and current density in the superconductor, and the rapidly varying material properties at cryogenic temperatures. In this paper, the behavior of superconducting coils during over-currents is discussed and a simplified capability curve is described to help standardize device capabilities. These curves are necessary to aid power system designers in appropriately designing the system and associated protection systems.      

Study on a Series Resistive SFCL to Improve Power System Transient Stability: Modeling, Simulation, and Experimental Verification

This paper presents a study to determine the optimal resistive value of a superconducting fault-current limiter (SFCL) for enhancing the transient stability of a power system more effectively. A resistive type of SFCL, which provides quick system protection, is modeled. Then, the optimal resistive value of the SFCL connected in series with a transmission line during a short-circuit fault is systematically determined by applying the equal-area criterion based on the power-angle curves. To verify the effectiveness of the optimal value of the proposed SFCL for reducing the value of fault current, several case studies are carried out by both simulation and experimental tests, particularly including the 220-V/300-A-scale laboratory and 13.2-kV/630-A-scale distribution system hardware tests. The results show that the optimal resistive value of the SFCL determined by the proposed method improves effectively the transient stability and damping performances during a fault over the other values determined by an ad hoc approach.      

Switching properties of a hybrid type superconducting fault currentlimiter using YBCO stripes

Presents investigations of a hybrid type superconducting fault current limiter (SFCL), which consists of transformers and resistive superconducting switches. The secondary windings of the transformer were separated into several electrically isolated circuits and linked inductively with each other by mutual flux, each of which has a superconducting current limiting unit of YBa₂Cu₃O ₇ (YBCO) stripes as a switch. Simple connection in series of the SFCL switches tends to produce ill-timed switching because of power dissipation imbalance between SFCL units. Both electrical isolation and mutual flux linkage of the switches provides a solution to power dissipation imbalance, inducing simultaneous switching by independent quenches and current redistribution of the YBCO films. This design enables increase of voltage ratings of SFCL with given YBCO stripes     

Fabrication of HTS dc Bias Coil for 35kV/90MVA SFCL

For a saturated iron core fault current limiter, superconductor is the only suitable material to make the dc bias coil, especially when the device is used in a high voltage power grid. Commonly, superconducting wires are used to wind the dc bias coil. Since the performance of the wires changes greatly under magnetic fields, the calculation of the field spatial distraction is essential to the optimization of the superconducting magnet. A superconducting coil with 141000 ampere-turns magnetizing capacity made of 17600 meters of BSCCO 2223 HTS tapes was fabricated. This coil was built for a 35kV/90MVA saturated iron-core fault current limiter. Computer simulations on magnetic field distribution were carried out to optimize the structural design, and experiments were done to verify the performance of the coil. The configuration and the key parameters of the coil will be reported in this paper.     

Superconducting FCL: design and application

Design, parameters, and application areas of a superconducting fault current limiter (FCL) are analyzed on the basis of the requirements of power systems. The comparison of resistive and inductive designs is carried out. An example of the effective application of FCLs in distribution substations is considered and the gain from the FCL installation is discussed. It is shown that an FCL not only limits a fault current but also increases the dynamic stability of the synchronous operation of electric machines. The calculation procedure of the parameters of an inductive FCL for a specific application case is described.     

Fabrication of HTS dc Bias Coil for 35 kV/90 MVA SFCL

Abstract---For a saturated iron core fault current limiter, superconductor is the only suitable material to make the dc bias coil, especially when the device is used in a high voltage power grid. Commonly, superconducting wires are used to wind the dc bias coil Since the performance of the wires changes greatly under magnetic fields, the calculation of the field spatial distraction is essential to the optimization of the superconducting magnet. A superconducting coil with 141000 ampere-turns magnetizing capacity made of 17600 meters of BSCCO 2223 HTS tapes was fabricated. This coil was built for a 35 kV/90 MVA saturated iron-core fault current limiter. Computer simulations on magnetic field distribution were carried out to optimize the structural design, and experiments were done to verify the performance of the coil The configuration and the key parameters of the coil will be reported in this paper.     

Feasibility of electric power transmission by DC superconducting cables

The electrical characteristics of dc superconducting cables of two power ratings were studied: 3 GW and 500 MW. Two designs were considered for each of the two power ratings. In the first design, the SUPPLY stream of the cryogen is surrounded by the high-voltage high-temperature superconductor cylinder. The RETURN stream of the cryogen is on the grounded side of the system. In the second design, both the SUPPLY and the RETURN streams of the cryogen are on the grounded side of the cable. Two electrical characteristics of these cables were studied: 1) fault currents and 2) current harmonics. It was concluded that neither the fault currents nor the current harmonics pose any problems in the operation of the dc superconducting cables.     

Performance of an inductive fault current limiter employing BSCCOsuperconducting cylinders

Inductive fault current limiters operating at high levels of short-circuit currents are plagued by appearance of overheated thermal domains in active superconducting elements. Excessive growth of thermal domains may lead to a fatal mechanical destruction of the superconducting element during a fault event. It has been determined that employment of superconductors with gradual dissipation onset controlled by flux relaxation processes can efficiently prevent local overheating. Operation of such elements, fabricated by melt cast technique, has been investigated experimentally in a small-scale open-core model of an inductive fault current limiter. The results of the experiments demonstrate the feasibility of application of superconducting cylinders having properties dominated by flux relaxation processes in inductive current limiters. The most important parameter of a superconducting element designated to operate in such devices is the rate of flux relaxation and its dependence on ac current amplitude. It has been found that ac losses associated with flux relaxation in the investigated cylinders allow for a reliable limiter operation at the nominal current level. Projection of the parameters of the investigated small-scale model to the full-scale device has been performed using the concept of physical modeling. The obtained results indicate that it is possible to build a full-scale device based on flux creep dissipation mechanisms for distribution networks     

Shunt active power filter synthesizing resistive loads

The paper discusses the use of a shunt active power filter to compensate for the line current distortion and to improve the power factor. The advantages of the resistive load synthesis over the sinusoidal current synthesis when the filter is used in a system where the voltage is not perfectly sinusoidal are presented. The control circuit is based on analogic multipliers, and the currents follow the same waveforms of the respective line voltages. Experimental results of connecting a three-phase active power filter to a nonsinusoidal grid are presented     

Large system interaction characteristics of superconductinggenerators

Differences between superconducting generators and conventional machines are identified, and ways in which superconducting machines will offer both advantages and problems are shown. Superconducting generators will have system interaction characteristics, somewhat different from those of their conventional counterparts. In general, superconducting machines will improve characteristics of the power system; their low reactances and long time constants will improve transient stability and voltage regulation. However, these also produce large fault currents and torques. If care is not taken, these machines may product interesting and perhaps destructive resonant effects on shaft lines. The author builds simple models that allow several important system integration characteristics of synchronous machines, including the differences between conventional and superconducting machines, to be discussed and understood. These include reactive power capability, transient stability, damping, voltage control, fault currents, and torques     

The analysis of the fault currents according to core saturation andfault angles in an inductive high-Tc superconducting fault currentlimiter

In this paper, we investigate the fault currents in an inductive high-Tc superconducting fault current limiter (SFCL). The currents can cause serious damage to the reliability and stability of the power system. To analyze the transient fault characteristics of the SFCL, we fabricated an inductive high-Tc SFCL and tested it under different fault conditions. To simulate a fault condition, a fault angle controller was connected to a load. As the firing angle of the triac in the fault angle controller was controlled, various angles of the fault instant can be selected. An important parameter for the design and the fabrication of the SFCL is the reduction of the fault currents. If abnormally high currents due to low impedance of SFCL do not occur in the network with SFCL, the currents flowing under fault conditions can be limited to a desired value within one cycle. The fault current reduction depends on saturation, normal zone propagation velocity, turns ratio, and the fault angle (the instant of the fault occurrence within a cycle)     

Kurzschlussstrom-Begrenzung mittels Bi2212-Hochtemperatur-Supraleitern — Stand der Forschung

Limiting fault currents by means of superconducting current limiters has been topic of intensive international research for many years. Superconducting current limiters make use of the super-conducter’s transition from superconducting to normal conducting state, and therefore it works like a nonlinear resistance. Due to its intrinsic physical proterties the superconducting current limiter comes close to an ideal limiter.     

Read operation performance of large selectorless cross-point array with self-rectifying memristive device

Memristive device based passive crossbar arrays hold a great promise for high-density and non-volatile memories. A significant challenge of ultra-high density integration of these crossbars is unwanted sneak-path currents. The most common way of addressing this issue today is an integrated or external selecting device to block unwanted current paths. In this paper, we use a memristive device with intrinsic rectifying behavior to suppress sneak-path currents in the crossbar. We systematically evaluate the read operation performance of large-scale crossbar arrays with regard to read margin and power consumption for different crossbar sizes, nanowire interconnect resistances, ON and OFF resistances, rectification ratios under different read-schemes. Outcomes of this study allow improved understanding of the trade-off between read margin, power consumption and read-schemes. Most importantly, this study provides a guideline for circuit designers to improve the performance of oxide-based resistive memory (RRAM) based cross-point arrays. Overall, self-rectifying behavior of the memristive device efficiently improves the read operation performance of large-scale selectorless cross-point arrays.     

Defect Simulation Methodology for iDDT Testing

The International Technology Roadmap for Semiconductors (ITRS) identifies two main challenges associated with the testing of manufactured ICs. First, the increase in complexity of semiconductor manufacturing process, physical properties of new materials, and the constraints imposed by resolution of lithography techniques etc., give rise to more complex failure mechanisms and hard-to-model defects that can no longer be abstracted using traditional fault models. Majority of defects, in today's technology, include resistive bridging and open defects with diverse electrical characteristics. Consequently, conventional fault models, and tools based on these models are becoming inadequate in addressing defects resulting from new failure mechanisms. Second, the defect detection resolution of main-stream I_DDQ testing is challenged by significant elevation in off-state quiescent current and process variability in newer technologies. Overcoming these challenges demands innovative test solutions that are based on realistic fault models capable of targeting real defects and thus, providing high defect coverage. In prior works power supply transient current or i_DDT testing has been shown to detect resistive bridging and open defects. The ability of transient currents to detect resistive opens and their insensitivity (virtually) to increase in static leakage current make i_DDT testing all the more attractive. However, in order to integrate i_DDT based methods into production test flows, it is necessary to develop a fault simulation strategy to assess the defect detection capability of test patterns and facilitate the ATPG process. The analog nature of the test observable, i.e., i_DDT signals, entail compute intensive transient simulations that are prohibitive. In this work, we propose a practical fault simulation model that partitions the task of simulating the DUT (device under test) into linear and non-linear components, comprising of power/ground-grid and core-logic, respectively. Using divide-and-conquer strategy, this model replaces the transient simulations of power/ground-grid with simple convolution operations utilizing its impulse response characteristics. We propose a path isolation strategy for core-logic as a means of reducing the computational complexity involved in deriving i_DDT signals in the non-linear portion. The methodology based on impulse response functions and isolated path simulation, can enable i_DDT fault simulation without having to simulate the entire DUT. To our knowledge, no practical technique exists to perform fault simulation for i_DDT based methods. The proposed fault simulation model offers two main advantages, first, it allows fault induction at geometric or layout level, thus providing a realistic representation of physical defects, and second, the current/voltage profile of power/ground-grid, derived for i_DDT fault simulation, can be used to perform accurate timing verification of logic circuit, thus facilitating design verification. In summary, the proposed fault simulation framework not only enables the assessment of defect detection capabilities of i_DDT test methodologies, but also establishes a platform for performing defect-based testing on practical designs.     

Modeling Thermal Process in a Resistive Element of a Fault Current Limiter

The thermal regime of the Ni tape immersed into liquid nitrogen and heated up due to Joule losses generated by a step-like direct current is studied experimentally and theoretically. The temporal dependence of the temperature rise in Ni tape is measured. An adiabatic approach is shown to give a conservative result. According to our results, taking into account the heat transfer by thermal conduction into liquid nitrogen is necessary. This circumstance allows one to reduce a significantly necessary amount of high-temperature-superconductor material for the superconducting part of a resistive fault current limiter.     

Operational characteristics of a flux-lock-type high-T/sub c/ superconducting fault current limiter with a tap changer

The authors investigate the operational characteristics of a flux-lock-type high-T/sub c/ superconducting (HTSC) fault current limiter (SFCL) with a tap changer which could adjust the number of turns of the third winding. In the case of conventional flux-lock-type SFCL, the phase adjusting capacitor is connected in series with magnetic field coil to adjust the magnetic field applied to the HTSC element in phase with the current flowing through the HTSC element during a fault time. However, the current flowing at the third winding, which is connected with magnetic field coil, affects the fault current limiting characteristics. To analyze the influence of current flowing at the third winding on the fault current limiting characteristics, the fault current limiting characteristics of the flux-lock type SFCL, whose inductance of coil 3 could be adjustable through a tap changer, are investigated through the experiments and the computer-aided simulations. The relation of line currents flowing into the flux-lock-type SFCL during a fault time and numbers of turns of a tap changer is drawn.     

Analysis of a passive superconducting fault current limiter

An analysis was carried out to predict the forced response of the equivalent circuit of an innovative superconducting fault current limiter (FCL). The FCL employs two superconducting coils with differing critical currents wound noninductively. The analysis shows that to reduce the voltage drop under normal operating conditions, the coupling coefficient should be kept fairly high (k>0.90). For a given coil configuration (ωL¯=constant), the limiting capability of the device increases with the resistance R of the trigger coil up to a certain value of R, then further increase in R changes very little the limiting capability of the FCL. However, further increase in R can reduce the heat generation rate in the device which will help alleviate the problem of relatively long recovery time. The fault current predicted from estimated values of R compares fairly well with results of an experiment reported in the literature. The discrepancy between the predicted and measured current is due mainly to the uncertainty in the estimated resistance R, because both the purity of Cu and the percentage of Cu in CuNi are not known. By varying the ratio of NbTi-Cu-CuNi in the matrix, the purity of Cu, and the percentage of Cu in CuNi various values of R, can be achieved, which should help to alleviate the problem of excessive Joule heating and recovery time     

Superconducting contacts

The microscopic size of the contact between two crossed superconducting wires offers a practical way to make a class of superconducting devices which are operated at high speed by very small currents. The critical current through the contact can be modulated by a current flowing along one or both of the crossed superconductors. Several device possibilities are presented.     

Sensitivity limitation of a SQUID gravity gradiometer due toelastic interaction between sensing currents and test masses

Differential displacement due to a gravitational force gradient, acting on two superconducting test masses which are elastically suspended from the instrument frame, is sensed by a superconducting quantum interference device (SQUID) coupled to the masses by a current flowing in the sensing circuits. An elastic interaction between the sensing currents and the currents mirrored on the superconducting surfaces of the test masses can stiffen the movement of the masses, reducing the sensitivity of the instrument. However, this interaction is not principally limiting, and the SQUID can be built so that stiffening does not occur