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1.
Die size reductions can be achieved through “optical shrinks,” compaction of existing layouts, or redesigns to finer fab geometries. For some die the limiting factors for die size reduction are bond pad pitch and bond pad size. In these “pad limited” designs, the circuitry is concentrated in the center of the die. Precious empty space exists between the bond pads in the periphery of the die and the circuitry in the die core. The only hope for die size reductions in these designs lies in advances in assembly technology that allow for reductions in bond pad pitches and bond pad size. Fine pitch assembly poses a number of challenges for conventional wire bond technology. Reducing bond pad pitch increases the probability of ball shorting, bond wire shorting, and bond wire damage. On the other hand, decreasing the die size by reducing the bond pad pitch results in longer wire lengths thus limiting some assembly options such as moving to smaller diameter bonding wires. Wire loop profile becomes a critical factor for control in fine pitch assembly. In this paper a statistical design of experiment is used in developing a wire bond loop profile control. The effect of major bonding parameters, such as kink-height, reverse loop, loop factor, wire tension, and their impact on loop profile are analyzed. The results obtained define the bond parameter requirements that must be met in order to control the wire loop profile to optimize fine pitch wire bond assembly yields  相似文献   

2.
多层芯片应用中的封装挑战和解决方案   总被引:3,自引:0,他引:3  
The continuous growth of stacked die packages is resulting from the technology‘s ability to effectively increase the functionality and capacity of electronic devices within the same footprint as a single chip.The increased utilization of stacked die packages in cell phone and other consumer products drives technologies that enable multiple die stacks within a given package dimension.This paper reviews t6he technology requirements and challenges for stacked die packages.Foremost among these is meeting package height is 1.2mm for a single die package.For stacked die packages,two or more die need to fit in the same area.That means every dimension in the package has to decrease,including the die thickness.the mold cap thickness,the bond line thickness and the wire bond loop profile.The technology enablers for stacked die packages include wafer thinning,thin die attachment,low profile wire bonding,bonding to unsupported edges and low sweep molding.  相似文献   

3.
论述了在叠层芯片封装的市场需求和挑战。首先采用在LQFP一个标准封装尺寸内,贴装2个或更多的芯片,这就要求封装体内每一个部分的尺寸都需要减小,例如芯片厚度、银胶厚度,金丝弧度,塑封体厚度等,要求在叠层封装过程中开发相应的技术来解决上述问题。重点就芯片减薄,银胶控制,无损化装片,立体键合,可靠性等进行了详细的介绍。  相似文献   

4.
In this study the degradation and reliability of a plastic encapsulated RF switching device were assessed by comparing several lots of a device that came directly off the assembly line to several other lots which had been subjected to accelerated stress testing. Comparisons of the structure, die and wirebonds were based on the results of examinations using optical microscopy, X-ray analysis, scanning acoustic microscopy, environmental scanning electron microscopy and wire bond pull tests.  相似文献   

5.
Direct gold and copper wires bonding on copper   总被引:1,自引:0,他引:1  
The key to bonding to copper die is to ensure bond pad cleanliness and minimum oxidation during wire bonding process. This has been achieved by applying a organic coating layer to protect the copper bond pad from oxidation. During the wire bonding process, the organic coating layer is removed and a metal to metal weld is formed. This organic layer is a self-assembled monolayer. Both gold and copper wires have been wire-bonded successfully to the copper die even without prior plasma cleaning. The ball diameter for both wires are 60 μm on a 100 μm fine pitch bond pad. The effectiveness of the protection of the organic coating layer starts from the wafer dicing process up to the wire bonding process and is able to protect the bond pad for an extended period after the first round of wire bond process. In this study, oxidization of copper bond pad at different packaging processing stages, dicing and die attach curing, have been explored. The ball shear strength for both gold and copper ball bonds achieved are 5 and 6 g/mil2 respectively. When subjected to high temperature storage test at 150 °C, the ball bonds formed by both gold and copper wire bond on the organic coated copper bondpad are thermally stable in ball shear strength up to a period of 1440 h. The encapsulated daisy chain test vehicle with both gold and copper wires bonding have passed 1000 cycles of thermal cycling test (−65 to 150 °C). It has been demonstrated that orientation imaging microscopy technique is able to detect early levels of oxidation on the copper bond pad. This is extremely important in characterization of the bondability of the copper bond pad surface.  相似文献   

6.
Data are presented comparing 1-percent MgAI wire with 1-percent SiAI wire for ultrasonically bonded interconnects on semiconductor devices. The effects of annealing time and temperature on the strength of the wire demonstrate the mechanical superiority of the 1-percent MgAI wire. The effects of ultrasonic power and time on wire deformation and bond pull strength demonstrate similar behavior for both the 1-percent MgAI wire and the 1-percent SiAI wire. It is also shown that there is a critical amount of wire deformation necessary for a strong bond, and that further deformation weakens the interconnection. Although there are very few data on the effects of Mg in Si, there have been fragmentary reports that 1-percent MgAI wire causes degradation of transistor characteristics. This investigation indicates that 1-percent MgAI wire is not the dominant degradation mechanism in any device studied.  相似文献   

7.
The wire bondability of Au-Ni-Cu bond pads with different Au plating schemes, including electrolytic and immersion plates, are evaluated after plasma treatment. The plasma cleaning conditions, such as cleaning power and time, are optimized based on the process window and wire pull strength measurements for different bond pad temperatures. Difference in the efficiency of plasma treatment in improving the wire bondability for different Au plates is identified. The plasma-cleaned bond pads are exposed to air to evaluate the recontamination process and the corresponding degradation of wire pull strength. The changes in bond pad surface characteristics, such as surface free energy and polar functionality, with exposure time are correlated to the wire pull strength, which in turn provides practical information about the shelf life of wire bonding after plasma cleaning.  相似文献   

8.
文章分析了一例采用金丝热超声键合电路在工艺监控过程中的键合强度检测合格,在高温稳定性烘焙后其引线抗拉强度同样符合MIL-STD-883G方法2011.7的要求,但电路在使用中出现第一顺序键合引脚开路现象。经分析是由于芯片键合区(压点)的材料、结构、键合工艺参数处于工艺下界,以及此类缺陷不能通过键合引线抗拉强度在线监测(包括125℃下的24h高温贮存后的检测)检测出而导致。最后针对缺陷所在,通过改进检测方法、键合工艺设置等消除了键合缺陷,并提高了键合可靠性。  相似文献   

9.
In this paper design rules for maximum current handling capability of gold bond wires are derived based on two failure mechanisms: (1) fusing of the wire; and (2) degradation of the interface between gold bond balls and the aluminum bond pads under high current/high temperature stress. For determination of the fuse current as a function of the length an analytical model is used to calculate the temperature and power distribution in the wire as a function of the position. The current level at which the melt temperature of gold is reached is the fuse current. The degradation mechanism under high current stress (up to 2.5 A) was studied by in-situ monitoring of the gold bond ball–aluminum interconnect contact resistance under high current stress at various temperatures and stress currents. The cumulative failure distributions were used to fit a model for lifetime as a function of current and temperature that shows an order of magnitude difference in lifetime between positive and negative current stress. Finally, fuse current and the lifetime model result in data-driven high current design rules for bond pad and wire.  相似文献   

10.
《Microelectronics Reliability》2014,54(9-10):2006-2012
The effect of bonding parameters on the reliability of thick Al wire bond is investigated. Samples were prepared with 25 different designs with 5 different bonding parameters such as time, ultrasonic power, begin-force, end-force and touch-down steps (pre-compression) with 5 levels. The bond signals of ultrasonic generator were collected during bonding in order to obtain prior quality information of bonded wires. 3D X-ray tomography was then used to evaluate bond quality during passive thermal cycling between −55 °C and 125 °C. Tomography datasets were obtained from the as-bonded condition and during cycling. The results clearly show ultrasonic power, appropriate levels of begin-force and touch-down steps are all important for achieving a well attached and reliable bond. Analysis of the virtual cross-sections indicates a good correlation between the bond signal (i.e. the initial bond quality) and wire bond damage/degradation rate. An improved understanding of the wire bonding process was achieved by observing the effect of the complex interaction of bonding parameters on the ultrasonic generator signals and degradation rate under thermal cycling.  相似文献   

11.
Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.  相似文献   

12.
A 60 GHz low-loss wideband interconnection of a CMOS transmitter and its antenna is presented in this paper. The integrated transmitter consists of an all-digital phase-locked loop (ADPLL) IC chip and a U-slot patch antenna connected through wire bonding and compensation matching circuit to operate in the 57–63 GHz frequency band. The system is implemented on a sandwiched printed circuit board (PCB) comprising FR4 to embed the ADPLL and the high-frequency Rogers laminate RO4350B for the antenna and the matching network. The matching circuit is designed in two configurations microstrip and grounded coplanar waveguide (GCPW) to compensate for the wire bond inductance. The capability and sensitivity of these two topologies considering the wire bond geometry variations are compared which points out that GCPW is more robust to wire bonding parasitic effects. Finally, the GCPW matching circuit is fabricated and interconnected to the ADPLL die and its performance is examined using hybrid simulation/measurement data.  相似文献   

13.
《Microelectronics Reliability》2014,54(9-10):1995-1999
High temperature storage lifetime tests of palladium coated copper bond wires (pcc-wires) beyond 1000 h@150 °C lead to an increased number of broken stitches during wire bond pull test. In this article we show that there is an intrinsic degradation of pcc-wires: defects in the Pd layer allow a temperature driven diffusion of Cu to the Pd surface reacting to CuO on the wire surface. Voids in the range of several microns in the Cu wire core weaken the bond wire strength to very low values.The degradation mechanism of pcc-wires is found in both cases, in molded packages and at non-molded wires from the spool. We present results after temperature storage at 150 °C, 175 °C, 200 °C, and 250 °C up to 3000 h.  相似文献   

14.
Bond degradation of Au wire/Al pad has become a major problem, because of the use of molding resin with low thermal stability (e.g. bi-phenyl epoxy resin) and the use of the IC devices under high thermal environments. It is therefore important to insure the thermal reliability at Au/Al bonds. The lifetime to bond failure of bi-phenyl epoxy molding became shorter than that for cresol novolac epoxy. The failures were caused by the corrosion reaction of Au–Al intermetallics with bromine (Br) contained in the resin compounds. It was clarified that the reactive intermetallic was Au4Al phase formed in the bond interface.The governing factors of the bond corrosion were investigated such as resin compound and gold wire material. Especially some impurities in gold wire could affect the Au–Al intermetallic growing and therefore retard the corrosion. The use of the alloyed wire was effective in improving the bond reliability.  相似文献   

15.
Wire-bonded chip-on-board (CoB) multi chip modules consist of die and bond wires that are encapsulated to protect them from mechanical and chemical damage. This paper describes a rapid-assessment model for the prediction of thermomechanical strains developed in the encapsulated ball-wedge bond wires due to thermal expansions experienced during curing or subsequent environmental changes. The wire profile is modeled using a piece-wise continuous polynomial function (cubic spline) with appropriate boundary conditions at the two bond sites. Plastic deformation is ignored in the current analysis as a first-order approximation. Then a 2D Raleigh-Ritz (RR) model is developed to estimate the thermomechanical stresses in the bond wire due to temperature cycling in the presence of an encapsulant. The purpose of the model is to provide a rapid ranking of the thermomechanical robustness of different wire-bond design options. Results are validated by detailed 2D finite element analysis (FEA) and are compared to fatigue failure data available from thermal cycling tests.  相似文献   

16.
Ultrasonic ball or wedge bonding of Au or Al has been the traditional method for mak-ing electrical interconnects between die and chip header for most Integrated Circuit (IC) and microsensor devices. Electrical interconnections made from these materials may, however, be unsuitable for some device applications. Some microsensors (e.g., oxygen exhaust gas sensors) can be subject to temperatures as high as 900° C in both oxidizing and reducing atmospheres, conditions for which the properties of Au or Al are unsuit-able. In this report we describe a new means of making electrical connections between die and chip header. Interconnects are made by using a conventional wire bonder to ultrasonically wedge bond 0.032 mm diameter Pt wires to both Pt and Al thin films. Interconnects made in this manner are remarkably strong, as compared with Au wire bonds, with pull strengths of ∼13 g. Electrical measurements show contact resistances of ≲0.05 Ω. Annealing tests show that bonds made to thin metal films of Pt on Ti on sapphire show no appreciable signs of electrical or mechanical degradation after an-neals at 900° C for 1 h in pure oxygen.  相似文献   

17.
《Microelectronics Reliability》2014,54(9-10):1661-1665
This paper describes the use of in-situ High Temperature Storage Life (HTSL) tests based on a four point resistance method to evaluate Cu wire interconnect reliability. Although the same set up was used in the past to monitor Au–Al ball bond degradation, a different approach was needed for this system. Using conventional statistical methods of failure probability distributions and a fixed failure criterion were found to be unsuitable in this case. Besides this, tests usually take very long until a sufficient percentage of the population have failed according to that criterion. A simple physical model was used to electrically quantify ball bond degradation due to the prevailing failure mechanism in a substantially smaller amount of test time. The method enabled the determination of activation energies for a number of moulding compounds and is extremely useful for a fast screening of such materials regarding their suitability for Cu wire.  相似文献   

18.
An innovative theoretical model by altering cross section of gold wire is proposed to reinforce the wire sag stiffness of a wire bond that suffered low yield for the applications of 3-dimensional and multi-chip module (MCM) packaging. The flexural rigidity of a wire bond is found to be a function of the material properties in the moment of inertia of a bond wire. Suffice to say, if the moment of inertia of the bond wire can be raised, the associated sag deflection will be diminished. By manipulating the moment of inertia of the bond wire, the sag deflection of the wire bond can be regulated appropriately to avoid wire sag and even the wire sweep enigma. The ellipse-like cross section of a wire bond is applied as a numerical example to improve the wire sweep stiffness or wire sag stiffness in this study. The results show the sag deflection of a wire bond can be reduced significantly if the ellipse-like cross section is oriented in the preferred direction of flexural rigidity of a wire bond. Furthermore, a systematic study of matching design is performed to control wire sag and wire sweep for the wire bonding applications of overhang cross-stacked and step-stacked packaging. It shows that to use a single diameter of bonding wire in these complicate bonding environments of overhang stacked configurations is a favored possibility. The advantages shown from the theoretical study need to be implemented in further work in a production environment on current wire bonding equipment.  相似文献   

19.
A modular test chip comprising an array of 2 mm square modules has been designed and fabricated. The maximum chip size can be up to 10 mm square, i.e. a 5 × 5 array of modules. The motivation behind the test chip is primarily the need to address reliability concerns in the use of copper wire bonding. It is known that the move to replace gold wire bonding with copper, driven primarily by the escalating price of gold, leads to reliability challenges at the interfaces between the wire bonds, the bond pads and the mould compound. Its function is to address. The chip comprises daisy chain structures to monitor changes of wire bond resistance and leakage current, large and small area stress sensors to measure stress on the chip associated with die attach and moulding, and comb and triple track sensors to study corrosion and moisture penetration related to mould compound.  相似文献   

20.
This paper presents an experimental technique to characterize the damage evolution of the topside interconnections of power semi-conductor devices during power cycling tests. DC power cycling tests are done on Semikron SKIM 63 power modules, a solder-free module with silver sintered chips, ensuring the degradations to appear in the top layers only. The cycled substrates are then extracted from the test bench at different steps of the aging for analysis. Four-probe measurements are implemented on the chips so that the evolution of physical parameters representative of the degradation in the metallization and the bond wire contacts can be obtained. Finally, optical microscopy analysis of cross-sections at the wire bond contact interface is carried out to corroborate the electrical measurements to the crack length growth after specific aging intervals.  相似文献   

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