Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip

In this paper, experimental methods are emphatically described for measuring the proton single event effects (SEE) in Xilinx Zynq-7010 system-on chip. Experimental data are presented showing that low energy (3 MeV ≤ Energy ≤ 10 MeV) proton irradiation can cause single event effects in different hardware blocks of Xilinx Zynq-7010 SoC, including D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA). Moreover, the sensitivities of different hardware blocks to single event effects are different. Finally, the Stopping and Range of Ions in Matter (SRIM) software calculations show the possible reasons for this difference.     

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.     

A concise study of neutron irradiation effects on power MOSFETs and IGBTs

Over the past years there have been growing concerns on the adverse effects of atmospheric neutrons on power semiconductors even at sea level. In this paper we report recent results of neutron irradiation (1.9 MeV) experiments conducted on 650 V Super-Junction MOSFETs and Field-Stop Trench Insulated Gate Bipolar Transistors (IGBTs). The typical experiments found in literature which study the irradiation of power electronics chose a white line spectrum of neutron energies, ranging from 1 to 180 MeV; however, we have deliberately chosen to study the effect of monochromatic radiation of fast neutrons, as a first in a series of experiments, to better understand the full range of interactions from fast to ultra fast neutrons (100 MeV). We show that a multitude of failure modes already appear at neutron energies of 1.9 MeV ranging from gate oxide degradation to single event effects (SEE). Moreover an outstanding ruggedness of devices is demonstrated, which shows no failures at 80% rated break down and below under extreme aging conditions.     

High fluence 1.8 MeV proton irradiation effects on n-type MOS capacitors

MOS capacitors with 7 nm SiO₂ dielectrics and n-doped Si substrate were irradiated by 1.8 MeV protons with fluences ranging from 10¹² to 5 × 10¹³ cm^?2 which correspond to the typical LHC fluence range. No significant increase in gate oxide leakage current was detected. A decrease of the capacitance was observed in the accumulation regime. This effect is explained by an increase of the substrate resistivity caused by displacement damage.     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

Investigation of deep level defects in electron irradiated indium arsenide quantum dots embedded in a gallium arsenide matrix

Gallium arsenide diodes with and without indium arsenide quantum dots were electron irradiated to investigate radiation induced defects. Baseline and quantum dot gallium arsenide pn-junction diodes were characterized by capacitance–voltage measurements, and deep level transient spectroscopy. Carrier accumulation was observed in the gallium arsenide quantum dot sample at the designed depth for the quantum dots via capacitance–voltage measurements. Prior to irradiation, a defect 0.84 eV below the conduction band (E_C – 0.84 eV) was observed in the baseline sample which is consistent with the native EL2 defect seen in gallium arsenide. After 1 MeV electron irradiation three new defects were observed in the baseline sample, labeled as E3 (E_C – 0.25 eV), E4 (E_C – 0.55 eV), and E5 (E_C – 0.76 eV), consistent with literature reports of electron irradiated gallium arsenide. Prior to irradiation, the addition of quantum dots appeared to have introduced defect levels at E_C – 0.21, E_C – 0.38, and E_C – 0.75 eV denoted as QD–DX1, QD–DX2, and QD–EL2 respectively. In the quantum dot sample after 1 MeV electron irradiation, QD–E3 (E_C – 0.28 eV), QD–E4 (E_C – 0.49 eV), and QD–EL2 (E_C – 0.72 eV) defects, similar to the baseline sample, were observed, although the trap density was dissimilar to that of the baseline sample. The quantum dot sample showed a higher density of the QD–E4 defect and a lower density of QD–E3, while the QD–EL2 defect seemed to be unaffected by electron irradiation. These findings suggest that the quantum dot sample may be more radiation tolerant to the E3 defect as compared to the baseline sample.     

Twistable nonvolatile organic resistive memory devices

We fabricated an 8 × 8 cross-bar array-type organic nonvolatile memory devices on twistable poly(ethylene terephthalate) (PET) substrate. A composite of polyimide (PI) and 6-phenyl-C61 butyric acid methyl ester (PCBM) was used as the active material for the memory devices. The organic memory devices showed a high ON/OFF current ratio, reproducibility with good endurance cycle, and stability with long retention time over 5 × 10⁴ s on the flat substrate. The device performance remained well under the twisted condition with a twist angle up to ～30°. The twistable organic memory device has a potential to be utilized in more complex flexible organic device configurations.     

A low-complexity UWB RF receiver based on a novel low noise amplifier

A novel low-complexity ultra-wideband UWB receiver is proposed for short-range wireless transmission communications without considering multipath effect. The receiver chip uses a low-complexity UWB non-coherent receiving system solution with the core module composed of squarer and low-pass filter. By introducing asymmetric gate series inductance and RCL parallel negative feedback loop into the two-stage push–pull amplifier, the low-noise amplification and input impedance matching at ultra-wide bandwidth were achieved. With only two inductors and self-biased function, the chip area and power consumption can be saved largely. The proposed UWB receiver chip was fabricated in a 0.18 μm RF CMOS technology. Experimental results show that it can achieve a bandwidth of 3–5 GHz, maximum receiving symbol rate of 250 Mbps, receiving sensitivity of −80 dBm and power consumption of 36 mW, providing a low-complexity and high-speed physical implementation of the short-range high-speed wireless interconnection between electronic devices in the future.     

Thickness dependent barrier performance of permeation barriers made from atomic layer deposited alumina for organic devices

Organic devices like organic light emitting diodes (OLEDs) or organic solar cells degrade fast when exposed to ambient air. Hence, thin-films acting as permeation barriers are needed for their protection. Atomic layer deposition (ALD) is known to be one of the best technologies to reach barriers with a low defect density at gentle process conditions. As well, ALD is reported to be one of the thinnest barrier layers, with a critical thickness – defining a continuous barrier film – as low as 5–10 nm for ALD processed Al₂O₃. In this work, we investigate the barrier performance of Al₂O₃ films processed by ALD at 80 °C with trimethylaluminum and ozone as precursors. The coverage of defects in such films is investigated on a 5 nm thick Al₂O₃ film, i.e. below the critical thickness, on calcium using atomic force microscopy (AFM). We find for this sub-critical thickness regime that all spots giving raise to water ingress on the 20 × 20 μm² scan range are positioned on nearly flat surface sites without the presence of particles or large substrate features. Hence below the critical thickness, ALD leaves open or at least weakly covered spots even on feature-free surface sites. The thickness dependent performance of these barrier films is investigated for thicknesses ranging from 15 to 100 nm, i.e. above the assumed critical film thickness of this system. To measure the barrier performance, electrical calcium corrosion tests are used in order to measure the water vapor transmission rate (WVTR), electrodeposition is used in order to decorate and count defects, and dark spot growth on OLEDs is used in order to confirm the results for real devices. For 15–25 nm barrier thickness, we observe an exponential decrease in defect density with barrier thickness which explains the likewise observed exponential decrease in WVTR and OLED degradation rate. Above 25 nm, a further increase in barrier thickness leads to a further exponential decrease in defect density, but an only sub-exponential decrease in WVTR and OLED degradation rate. In conclusion, the performance of the thin Al₂O₃ permeation barrier is dominated by its defect density. This defect density is reduced exponentially with increasing barrier thickness for alumina thicknesses of up to at least 25 nm.     

Low energy ion beam machining of ULE® substrates: Evaluation of surface roughness

In order to apply ion beam figuring (IBF) to final shape correction of the substrates of projection optics for EUVL, ion beam machining characteristics such as high-spatial frequency roughness (HSFR) and mid-spatial frequency surface roughness (MSFR) of ULE^® substrate were investigated. Our previous research confirmed that the surface roughness of the ULE^® machined by Ar⁺ ion beam with energy of 3–10 keV decreases with decreasing the ion beam energy. Therefore, we have conducted our research on ion beam machining of ULE^® substrate by Ar⁺ ion beam with energy from 0.2 to 2 keV. The HSFR and MSFR of the mechanically pre-finished ULE^® substrate were 0.06 and 0.07 nm rms, respectively; whereas, the HSFR and MSFR of the substrate irradiated by Ar⁺ ion beam at energy of 0.3 keV were less than 0.10 and 0.08 nm rms, respectively. The HSFR is the best result among our previous and other current research.     

Thermal characteristics and fabrication of silicon sub-mount based LED package

In this paper, the cost of a light emitting diode (LED) package is lowered by using a silicon substrate as the base attached to the chip, in contrast to the conventional chip-on-board (COB) package. In addition we proposed an LED package with a new structure to promote reliability and lifespan by maximizing heat dissipation from the chip. We designed an LED package combining the advantages of COB based on conventional metal printed circuit board (PCB) and the merits of a silicon sub-mount as a substrate. When an input current 500–1000 mA was applied, the fabricated LED exhibited the light output of approximately 112 lm/W at 29 W. We also measured and compared the thermal resistance of the sub-mount package and conventional COB package. The measured thermal resistance of the sub-mount package with a reflective film of Ag and the COB package were 0.625 K/W and 1.352 K/W, respectively.     

Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65 nm technology platform

The purpose of this work was to study the influence of different layout parameters on the electrical performances and Time-To-Latch-Up (TTLU) by means of the injection of substrate current on SCR devices to be used as ESD protection structures for the 65 nm Flash memory technology platform. Low (1.2 V) and high (5.0 V) voltage class devices were studied in DC and 100 ns TLP regimes, and an ad hoc setup was developed to investigate TTLU as a function of the injected current needed to Latch-Up HV-SCRs. Results were then compared to 2D device simulations.     

The role of electronic energy loss in SHI irradiated Ni/oxide/n-GaP Schottky diode

The impact of energy loss mechanism by 100 MeV Au^8 + ion on the dielectric parameters of Ni/oxide/n-GaP Schottky diode was studied under different fluences. The Schottky barrier height, donor ion concentration and interface states density of the diode were varied considerably under different ion fluence. The various dielectric parameters were altered significantly by the ion fluence. The reduction in dielectric constant after irradiation was ascribed to screening of space charge polarization due to reduction in interface states density. The relaxation peak of imaginary electric modulus indicates hopping type conduction mechanisms in the intermediate voltage range. The sensitive behavior of dielectric parameters with fluence dose was attributed to the alteration of interface state density due to high electronic energy loss of 100 MeV Au^8 + ions at the interface.     

Brush electrodeposited silver indium selenide films and their optical characteristics

Silver indium selenide films were brush electrodeposited on tin oxide coated glass substrates at different substrate temperatures. The films were single phase with chalcopyrite structure. Optical absorption measurements indicated a band gap in the range of 1.20–1.30 eV with decrease of substrate temperature. Transmission spectra exhibited interference fringes. Using the envelope method, calculated values of refractive index at 850 nm decreased from 3.53 to 2.62 with decrease of substrate temperature. From the refractive index data, the value of N/m^⁎ was estimated to be in the range of 0.89–1.22. Optical data were analyzed by the single-effective oscillator model, and the single oscillator energy as well as the dispersion energy was estimated. The single oscillator energy decreased from 1.83 eV to 1.68 eV with the increase of substrate temperature. The dispersion energy increased from 5.42 eV to 12.25 eV with the increase of substrate temperature.     

Low-temperature low-pressure die attach with hybrid silver particle paste

New types of die attach pastes comprising micron-sized Ag particles hybridized with submicron-sized Ag particles were considered as lead-free die attach materials for SiC power semiconductors. Micron-sized Ag particles in alcohol solvent were prepared by mixing the die attach paste with submicron-sized Ag particles. The alcohol vaporizes completely during sintering and no residue exists in the bonding layer. The Ag layer has a uniform porous structure. The electrical resistivity of the printed tracks decreases below 1 × 10^?5 Ω cm when sintered above 200 °C. When sintered at 200 °C for 30 min, the average resistivity reaches 5 × 10^?6 Ω cm, which is slightly higher than the value obtained by using Ag nanoparticle paste. A SiC die was successfully bonded to a direct bonded copper substrate and the die-shear strength gradually increases with the increase in bonding temperature up to 300 °C. The Ag die attach bond layer was stable against thermal cycles between ?40 °C and 300 °C.     

Fabrication of nano-sized resist patterns on flexible plastic film using thermal curing nano-imprint lithography

Due to polymer’s excellent flexibility, transparency, reliability and light weight, it is a good candidate material for substrate of devices including organic electronic devices, biomedical devices, and flexible displays (LCD and OLED). In order to build such devices on polymer, nano- to micron-sized patterning must be accomplished. Since polymer materials reacts with organic solvents or developer solutions which are inevitably used in photolithography and cannot bear high temperature (∼140 °C) process for photoresist baking, conventional photolithography cannot be used to polymer substrate. In this research, monomer based thermal curing imprinting lithography was used to make as small as 100 nm dense line and space patterns on flexible PET (polyethylene-terephthalate) film. Compared to hot embossing lithography, monomer based thermal curing imprint lithography uses monomer based imprint resin which consists of base monomer and thermal initiator. Since it is liquid phase at room temperature and polymerization can be initiated at 85 °C, which is much lower than glass temperature of polymer resin, the pattern transfer can be done at much lower temperature and pressure. Hence, patterns as small as 100 nm were successfully fabricated on flexible PET film substrate by monomer based thermal curing imprinting lithography at 85 °C and 5 atm without any noticeable degradation of PET substrate.     

Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

Low power flexible organic thin film transistors with amorphous Ba0.7Sr0.3TiO3 gate dielectric grown by pulsed laser deposition at low temperature

We deposited amorphous Ba_0.7Sr_0.3TiO₃ (BST) on silicon and plastic substrate under 110 °C by pulsed laser deposition (PLD) and use it as the dielectric of the organic transistor. Depends on the thickness of BST layer, the highest mobility of the devices can achieve 1.24 cm² V^?1 s^?1 and 1.01 cm² V^?1 s^?1 on the silicon and polyethylene naphthalate (PEN) substrate, respectively. We also studied the upward and downward bending tests on the transistors and the dielectric thin films. We found that the BST dielectric pentacene transistor can maintain the mobility at 0.5 cm² V^?1 s^?1 or higher while the bending radius is around 3 mm in both upward and downward bending. Our finding demonstrates the potential application of PLD growth high-k dielectric in the large area organic electronics devices.     

Low energy Xe+ ion beam machining of ULE® substrates for EUVL projection optics – Evaluation of high-spatial frequency roughness

Ion beam figuring (IBF) is a suitable technology for the final shape correction of substrates used in the projection optics of EUVL tools. In order to achieve HSFR below 0.10 nm rms, we have conducted our research on ion beam machining of the ULE® substrate by Xe⁺ ion beam with energy less than 2 keV. The HSFR of the unprocessed ULE® surface was 0.06 nm rms, whereas the HSFR of the ULE® substrate machined by under 0.7 keV Xe⁺ ion beam was less than 0.08 nm rms. This HSFR (0.08 nm rms) is lower than that (0.10 nm rms) of the ULE® substrate machined with Ar⁺ ion beam. Therefore, Xe⁺ ion beam with energy under 0.7 keV can be used for figure error correction of the ULE® substrates for projection optics used in commercially available EUVL exposure tools.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.