Design of parallel concatenated convolutional codes

A parallel concatenated convolutional coding scheme consists of two constituent systematic: convolutional encoders linked by an interleaver. The information bits at the input of the first encoder are scrambled by the interleaver before entering the second encoder. The codewords of the parallel concatenated code consist of the information bits followed by the parity check bits of both encoders. Parallel concatenated codes (turbo codes), decoded through an iterative decoding algorithm of relatively low complexity, have been shown to yield remarkable coding gains close to theoretical limits. We characterize the separate contributions that the interleaver length and constituent codes give to the overall performance of the parallel concatenated code, and present some guidelines for the optimal design of the constituent convolutional codes     

Unveiling turbo codes: some results on parallel concatenated codingschemes

A parallel concatenated coding scheme consists of two simple constituent systematic encoders linked by an interleaver. The input bits to the first encoder are scrambled by the interleaver before entering the second encoder. The codeword of the parallel concatenated code consists of the input bits to the first encoder followed by the parity check bits of both encoders. This construction can be generalized to any number of constituent codes. Parallel concatenated schemes employing two convolutional codes as constituent codes, in connection with an iterative decoding algorithm of complexity comparable to that of the constituent codes, have been previously shown to yield remarkable coding gains close to theoretical limits. They have been named, and are known as, “turbo codes”. We propose a method to evaluate an upper bound to the bit error probability of a parallel concatenated coding scheme averaged over all interleavers of a given length. The analytical bounding technique is then used to shed some light on some crucial questions, which have been floating around in the communications community since the proposal of turbo codes     

Multilevel turbo coding with short interleavers

The impact of the interleaver, embedded in the encoder for a parallel concatenated code, called the turbo code, is studied. The known turbo codes consist of long random interleavers, whose purpose is to reduce the value of the error coefficients. It is shown that an increased minimum Hamming distance can be obtained by using a structured interleaver. For low bit-error rates (BERs), we show that the performance of turbo codes with a structured interleaver is better than that obtained with a random interleaver. Another important advantage of the structured interleaver is the short length required, which yields a short decoding delay and reduced decoding complexity (in terms of memory). We also consider the use of turbo codes as component codes in multilevel codes. Powerful coding structures that consist of two component codes are suggested. Computer simulations are performed in order to evaluate the reduction in coding gain due to suboptimal iterative decoding. From the results of these simulations we deduce that the degradation in the performance (due to suboptimal decoding) is very small     

A new high rate code scheme with highly parallel and low complexity decoding algorithm

A new high rate code scheme is proposed in this paper. It consists of serial concatenated recursive systematic ordinary (nonpunctured) convolutional codes with only 8 states in the trellis of the corresponding reciprocal dual codes. With a low complexity and highly parallel decoding algorithm, over additive white Gaussian noise channels, the proposed codes can achieve good bit error rate (BER) performance comparable to that of turbo codes and low density parity check (LDPC) codes. At code rate R=16/17, the overall decoding complexity of the proposed code scheme is almost half that of the LDPC codes.     

一类性能好、复杂度低的纠错编码--乘加码

对一类性能好且复杂度低的纠错编码技术——乘加码进行了介绍。他是在单校验位的Turbo乘积码(Single Parity Check Turbo Product Code)的基础上改进而来的,即由单校验位的Turbo乘积码作为外码,码率为1的递归卷积码作为内码串行级联而成。介绍了乘加码的编码方式和译码方法,并给出了其性能分析。对于一定的分组长度,这类码表现出与Turbo码相近的性能,但其译码复杂度要远远低于Turbo码。     

Turbo-SPC codes

This letter is concerned with a family of modified turbo-type codes, referred to as turbo-SPC (single parity check) codes. A technique based on the SPC code is introduced to replace puncturing for rate adjustment. A noticeable feature of the proposed scheme is the significantly reduced decoding complexity compared with the standard punctured turbo code. The cost reduction factor becomes more noticeable as rate increases (over ten times for rate →1). The error-rate floor problem known to turbo codes can also be improved using the proposed scheme. For moderate to high rates, performances of about 0.5 dB from the theoretical limits at BER=10^-5 have been observed for turbo-SPC codes     

Concatenated codes for fading channels based on recursive space-time trellis codes

We propose a class of codes which combine the principles of turbo coding and space-time trellis codes. It is first shown that several classes of space-time codes have an equivalent recursive realization. This fact is then exploited to design serial concatenated coding schemes with an outer code, interleaver, and an inner recursive space-time encoder. Two solutions are proposed in this paper - the use of convolutional outer codes aimed mainly to improve the power efficiency and the use of very high-rate outer codes to obtain significant improvement in power efficiency with a marginal decrease in spectral efficiency. We show that single parity check based turbo product codes are a good candidate for very high-rate outer codes. Finally, we propose an automatic repeat request scheme based on recursive realizations of space-time codes and show that the proposed scheme provides significant reduction in frame error rate.     

Approaching Shannon performance by iterative decoding of linear codes with low-density generator matrix

We propose the use of linear codes with low density generator matrix to achieve a performance similar to that of turbo and standard low-density parity check codes. The use of iterative decoding techniques - message passing -over the corresponding graph achieves a performance close to the Shannon theoretical limit. As an advantage with respect to turbo and standard low-density parity check codes, the complexity of the decoding and encoding procedures is very low.     

The Effect of Block Interleaving in an LDPC‐Turbo Concatenated Code

The effect of block interleaving in a low density parity check (LDPC)‐turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed‐Solomon (RS) code. Thus, an LDPC‐turbo concatenated code can show better performance than the conventional RS‐turbo concatenated code. Furthermore, the performance of an LDPC‐turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.     

Low complexity concatenated coding schemes for digital satellite communications

A study of reduced complexity concatenated coding schemes, for commercial digital satellite systems with low-cost earth terminals, is reported. The study explored trade-offs between coding gain, overall rate and decoder complexity, and compared concatenated schemes with single codes. It concentrated on short block and constraint length inner codes, with soft decision decoding, concatenated with a range of Reed-Solomon outer codes. The dimension of the inner code was matched to the outer code symbol size, and appropriate interleaving between the inner and outer codes was used. Very useful coding gains were achieved with relatively high-rate, low-complexity schemes. For example, concatenating the soft decision decoded (9,8) single parity check inner code with the CCSDS recommended standard Reed-Solomon outer code gives a coding gain of 4.8dB at a bit error probability of 10^?5, with an overall rate of 0-78.     

Iterative decoding of parallel and serial concatenated single parity check product codes

An efficient, iterative soft-in-soft-out decoding scheme is employed for the parallel and serially concatenated single parity check (SPC) product codes, which has very low complexity, requiring only two addition-equivalent-operations per information bit. For a rate 0.8637 of parallel concatenated SPC product code, a performance of BER=10/sup -5/ at E/sub b//N/sub 0/=3.66 dB can be achieved using this decoding scheme, which is within 1 dB from the Shannon limit.     

Recent Advances in Turbo Code Design and Theory

The discovery of turbo codes and the subsequent rediscovery of low-density parity-check (LDPC) codes represent major milestones in the field of channel coding. Recent advances in the design and theory of turbo codes and their relationship to LDPC codes are discussed. Several new interleaver designs for turbo codes are presented which illustrate the important role that the interleaver plays in these codes. The relationship between turbo codes and LDPC codes is explored via an explicit formulation of the parity-check matrix of a turbo code, and simulation results are given for sum product decoding of a turbo code.     

A Bandwidth Efficient Turbo Coding Scheme for VDSL Systems

The current forward error correction (FEC) scheme for very high bit-rate digital subscriber line (VDSL) systems in the ANSI standard employs a 16-state four-dimensional (4D) Wei code as the inner code and the Reed-Solomon (RS) code as the outer code. The major drawback of this scheme is that further improvement cannot be achieved without a substantial increase in the complexity and power penalty. Also, a VDSL system employing the 4D Wei-RS scheme operates far below the channel capacity. In 1993, powerful turbo codes were introduced whose performance closely approaches the Shannon limit. In this paper, we propose a bandwidth and power efficient turbo coding scheme for VDSL modems in order to obtain high data rates, extended loop reach and increased transmission robustness. We also propose a pipelined decoding scheme to reduce the latency at the receiver end. The objective of the proposed scheme is to provide a higher coding gain than that given by the 4D Wei-RS scheme, resulting in an improved performance of the VDSL modems in terms of bit rate, loop length and transmitting power. The scheme is investigated for various values of transmitting power, signaling frequencies and numbers of crosstalkers for a targeted bit error rate of 10⁻⁵ and is implemented in a system with a quadrature amplitude modulation in which a mixed set partitioning mapping is employed to reduce the decoding complexity. The effects of code complexity, interleaver length, the number of decoding iterations and the level of modulation on the performance of VDSL modems are explored. Simulation results are presented and compared to those of the 4D Wei-RS scheme. The results show that the choice of turbo codes not only provides a significant coding gain over the standard FEC scheme but also efficiently maximizes the loop length and bit rate at a very low transmitting power in the presence of dominant far-end crosstalk and intersymbol interference. In order to compare the hardware complexity, we synthesize the proposed and 4D Wei-RS schemes using SYNOPSYS with the target technology of Xilinx 4020e-3. The Xilinx field programmable gate array statistics of the proposed scheme is compared with that of the 4D Wei-RS scheme.     

Product accumulate codes: a class of codes with near-capacity performance and low decoding complexity

We propose a novel class of provably good codes which are a serial concatenation of a single-parity-check (SPC)-based product code, an interleaver, and a rate-1 recursive convolutional code. The proposed codes, termed product accumulate (PA) codes, are linear time encodable and linear time decodable. We show that the product code by itself does not have a positive threshold, but a PA code can provide arbitrarily low bit-error rate (BER) under both maximum-likelihood (ML) decoding and iterative decoding. Two message-passing decoding algorithms are proposed and it is shown that a particular update schedule for these message-passing algorithms is equivalent to conventional turbo decoding of the serial concatenated code, but with significantly lower complexity. Tight upper bounds on the ML performance using Divsalar's (1999) simple bound and thresholds under density evolution (DE) show that these codes are capable of performance within a few tenths of a decibel away from the Shannon limit. Simulation results confirm these claims and show that these codes provide performance similar to turbo codes but with significantly less decoding complexity and with a lower error floor. Hence, we propose PA codes as a class of prospective codes with good performance, low decoding complexity, regular structure, and flexible rate adaptivity for all rates above 1/2.     

On turbo encodedBicm

The superior performance of the binary turbo codes has stimulated vigorous efforts in generating bandwidth efficient modulation schemes adhering to these codes. Several approaches for the integration of turbo-coding and modulation have emerged in recent years but none seem to dominate. In the bit interleaved coded modulation (Bicm) scheme is used to achieve high bandwidth and power efficiency, while separating coding and modulation. As is now well known, theBicm scheme achieves capacity remarkably close to the constellation channel capacity. The turbo-Bicm scheme enjoys high coding diversity (well suited for fading channels), high flexibility as well as design and implementation simplicity, while maintaining good power efficiency. The system comprises one standard turbo code, an interleaver, a mapper and a modulator at the transmitter, corresponding to a demodulator, a de-interleaver and a turbo decoder at the receiver. A modified system, which improves on performance by incorporating the demodulation in the iterative decoding procedure, is investigated, and some performance gain is demonstrated, especially for low rate codes. Information theoretic arguments for the somewhat minor potential improvement in performance are detailed. The preferred mapper and interleaver for this system are considered. Extending previous works, for higher level modulations, we analyze a system including a convolutional code, an interleaver, a differential encoder (De), a mapper and a modulator at the transmitter. As for theBpsk modulation, the serial concatenation of a convolutional code withDe outperforms the single convolutional code. The serial concatenation withDe approach is analyzed also for a turbo code, where it is found to fail in achieving performance improvement. Several structures for the serial concatenation withDe are examined. These results are substantiated through the ‘spectral thinning’ phenomena of the weight distribution of the convolutional and turbocodes.     

Iterative decoding for partial response (PR), equalized,magneto-optical (MO) data storage channels

Turbo codes and low-density parity check (LDPC) codes with iterative decoding have received significant research attention because of their remarkable near-capacity performance for additive white Gaussian noise (AWGN) channels. Previously, turbo code and LDPC code variants are being investigated as potential candidates for high-density magnetic recording channels suffering from low signal-to-noise ratios (SNR). We address the application of turbo codes and LDPC codes to magneto-optical (MO) recording channels. Our results focus on a variety of practical MO storage channel aspects, including storage density, partial response targets, the type of precoder used, and mark edge jitter. Instead of focusing just on bit error rates (BER), we also study the block error statistics. Our results for MO storage channels indicate that turbo codes of rate 16/17 can achieve coding gains of 3-5 dB over partial response maximum likelihood (PRML) methods for a 10^-4 target BER. Simulations also show that the performance of LDPC codes for MO channels is comparable to that of turbo codes, while requiring less computational complexity. Both LDPC codes and turbo codes with iterative decoding are seen to be robust to mark edge jitter     

On multiple slice turbo codes

The main problem with the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this problem by using a new family of turbo codes called Multiple Slice Turbo Codes. This family is based on two ideas: the encoding of each dimension with P independent tail-biting codes and a constrained interleaver structure that allows the parallel decoding of the P independent codewords in each dimension. The optimization of the interleaver is described. A high degree of parallelism is obtained with equivalent or better performance than thedvb-rcs turbo code. For very high throughput applications, the parallel architecture decreases both decoding latency and hardware complexity compared to the classical serial architecture, which requires memory duplication.     

一种基于奇偶校验码级联极化码的低复杂度译码算法

极化码作为一种纠错码,具有较好的编译码性能,已成为5G短码控制信道的标准编码方案.但在码长较短时,其性能不够优异.作为一种新型级联极化码,奇偶校验码与极化码的级联方案提高了有限码长的性能,但是其译码算法有着较高的复杂度.该文针对这一问题,提出一种基于奇偶校验码级联极化码的串行抵消局部列表译码(PC-PSCL)算法,该算...     

Improved space-time codes using serial concatenation

In this letter, a new family of space-time codes is proposed. These codes employ a serially concatenated coding scheme with a standard space-time code as the outer code and a very simple rate-1 recursive code as the inner code. Adding this simple rate-1 recursive inner code does not decrease the bit rate and introduces only negligible complexity increase to the transmitter when compared to cases with standard space-time codes. An interleaver is embedded between the inner coder and the outer coder and the size of this interleaver determines the performance gain. We also provide a relatively low complexity iterative decoding procedure. For applications which can tolerate delay, significant gain can be achieved with the proposed approach     

Turbo-coded optical direct-detection CDMA system with PPMmodulation

The performance of an optical code division multiple access (CDMA) system with turbo coding is analyzed and simulated. Turbo codes are parallel concatenated convolutional codes (PCCCs) in which the information bits are first encoded by a recursive systematic convolutional code, and then, after passing through an interleaver, are encoded by a second systematic convolutional encoder. Turbo coding is superimposed on an intensity-modulated optical channel with pulse-position modulation (PPM) and direct detection of the received optical signal, and the performance is evaluated in terms of an upper bound on bit error probability. From the simulation results, it is seen that turbo coding offers considerable coding gain over other methods, with reasonable encoding/decoding complexity. Also, it is demonstrated that, for a fixed code rate, the performance of the optical CDMA system can be substantially improved by increasing the interleaver length and the number of iterations. Serially concatenated convolutional codes (SCCCs) are also considered, and are shown to perform comparably to PCCC in general and better than PCCCs for the case of large signal photocounts. The results in this paper can be applied, for example, to indoor optical wireless LANs