Integrated electroplated micromachined magnetic devices using lowtemperature fabrication processes

Micromachining techniques are used to realize inductors and transformers integrated with a multichip package, allowing compact integration with chips, sensors, and other components. The processing steps chosen are all low-temperature, which allows the use of low cost substrates such as MCM-L compatible materials. A variety of micromachined inductors and transformers with different geometries and magnetic core materials are designed, fabricated, tested, and compared. Integrated permalloy and orthonol core inductors (15 μm thick) with nominally identical geometries of 4 mm×1.0 mm×0.13 mm and 30 turns of multilevel copper coils (40 μm thick) show differences in performance due to differences in core behavior. The permalloy core inductor has a slightly higher inductance, but it has much lower dc saturation current than the orthonol core inductor. The effect of insertion of a core air gap was also studied, Although inductors with no air gap having dimensions of 4 mm×4 mm×0.145 mm and 156 turns of multilevel electroplated copper coils (40 μm thick) and electroplated permalloy magnetic core (35 μm thick) have slightly higher inductance (about 1.5 μH), air gap inductors have much higher saturation current (180=250 mA). These devices have high current capability (up to 3 A steady dc current) and are suitable for low power converter applications     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

A comparison of two micromachined inductors (bar- and meander-type)for fully integrated boost DC/DC power converters

Two micromachined integrated inductors (bar- and meander-type) are realized on a silicon wafer by using modified, IC-compatible, multilevel metallization techniques. Efforts are made to minimize both the coil resistance and the magnetic reluctance by using thick electroplated conductors, cores, and vias. In the bar-type inductor, a 25-μm thick nickel-iron permalloy magnetic core bar is wrapped with 30-μm thick multilevel copper conductor lines. For an inductor size of 4 mm×1.0 mm×110 μm thickness having 33 turns of multilevel coils, the achieved specific inductance is approximately 30 nH/mm² at 1 MHz. In the meander-type inductor, the roles of conductor wire and magnetic core are switched, i.e., a magnetic core is wrapped around a conductor wire. This inductor size is 4 mm×1.0 mm×130 μm and consists of 30 turns of a 35-μm thick nickel-iron permalloy magnetic core around a 10-μm thick sputtered aluminum conductor lines. A specific inductance of 35 nH/mm² is achieved at a frequency of 1 MHz. Using these two inductors, switched DC/DC boost converters are demonstrated in a hybrid fashion. The obtained maximum output voltage is approximately double an input voltage of 3 V at switching frequencies of 300 kHz and a duty cycle of 50% for both inductors, demonstrating the usefulness of these integrated planar inductors     

A low-current Ku-band GaAs monolithic image rejectiondown-converter

A single-chip image rejection downconverter has been designed, fabricated. and tested for broadcast satellite receivers operating in the 11.7- to 12.2-GHz range. The downconverter consists of an RF low-noise amplifier (LNA), a filter-type image rejection mixer (IRM), and an intermediate frequency amplifier (IFA). It receives 11.7- to 12.2-GHz RF signals and down converts to 1.0- to 1.5-GHz IF signals with an external local oscillator. Since the filter integrated on the downconverter produces an image rejection of more than 30 dB, the downconverter requires no off-chip circuits for the image rejection. A conversion gain of 37±1 dB and a noise figure of less than 3.5 dB have been achieved over the RF frequency range. The current dissipation is only 40 mA, and the chip size is 2.8 mm×2.8 mm×0.45 mm     

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f_SR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q_max. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

CMOS source degenerated differential active inductor

A new CMOS source degenerated differential active inductor is proposed. The proposed differential active inductor required only six transistors or more for proper operation. It is very compact compared to a conventional differential active inductor that was design using two differential transconductors and which requires at least ten transistors. The proposed active inductor was fabricated using Silterra 0.18 mum CMOS process for demonstration. Measurement results show that the proposed active inductor has a wide tuning range with a maximum resonance frequency of 7.85 GHz.     

Large Q-factor improvement for spiral inductors on silicon using proton implantation

We have improved the Q-factor of a 4.6 nH spiral inductor, fabricated on a standard Si substrate, by more than 60%, by using an optimized proton implantation process. The inductor was fabricated in a 1-poly-6-metal process, and implanted after processing. The implantation increased the substrate impedance by /spl sim/ one order of magnitude without disturbing the inductor value before resonance. The S-parameters were well described by an equivalent circuit model. The significantly improved inductor performance and VLSI-compatible process makes the proton implantation suitable for high performance RF ICs.     

A New On-Chip Substrate-Coupled Inductor Model Implemented With Scalable Expressions

Accurate modeling of the on-chip inductor is essential for the design of high-speed, low-power, and low-noise radio-frequency integrated circuits. The conventional model has a measurable discrepancy as the current flowing in the substrate is not correctly considered. The substrate-coupled inductor model, however, considers the losses generated in both the vertical and horizontal directions. This model gives an intelligent explanation of the reduction in equivalent resistance between terminals with increasing frequency as well as the inductance and quality factor (Q-factor). In order to implement a fully scalable model, the circuit elements in the substrate-coupled inductor model are expressed as monomial equations in terms of physical geometry. These equations consider the physical implications of the parameters as well as employing a mathematical fit for extrapolation. Measurements are made on inductors fabricated using a standard 0.35-mum CMOS process and a 0.15-mum silicon-on-insulator CMOS process to successfully verify this model     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S₁₁ of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.     

A no-trimming SLIC two-chip set with coin telephone signalingfacilities

A subscriber line interface circuit (SLIC) two-chip set that eliminates off-chip functional trimming and integrates coin telephone set facilities as well as BORSCHT functions is described. The LSI chip set consists of (a) a subscriber interface IC fabricated using a 320-V dielectrically isolated bipolar process with on-chip thin-film resistors and double-layer metal, and (b) a subscriber processor IC with oversampling A-D/D-A converters and a microprogrammable digital signal processor (DSP), using a 1.6-μm CMOS process. Chip sizes are 5.5 mm×6.06 mm and 6.0 mm×5.7 mm, respectively. Using the two-chip set, an SLIC for a coin telephone set can be designed without using high-precision filter components or hybrid ICs with functional trimming     

A 400-mA current-mode buck converter with a self-trimming current sensing scheme

A current-programmed mode (CPM) controller is designed for improved DC–DC converter control. The key building block of the CPM controller is an accurate current-sensing circuit. This paper proposes a lossless current-sensing technique to measure the inductor current by measuring the current through the power transistor. A self-trimming circuit is used to compensate for any inaccuracies caused by voltage and temperature variations. The measurement results validate the operation of the fabricated chip.     

A 15-ns 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained     

Low Profile Integratable Inductor Fabricated Based on LTCC Technology for Microprocessor Power Delivery Applications

A novel low profile power inductor suitable for planar integration is designed and fabricated based on low temperature co-fired ceramics technology for microprocessor power delivery applications. The inductor was designed to operate at a switching frequency of 4 to 5MHz, carrying a nominal dc current of 20A with a ripple current of 8 to 10A in a 5-V to 1-V dc-dc converter. The design and fabrication procedure is discussed in this paper, followed by small signal measurement and magnetic characterization results. The inductor was implemented in a prototype converter and the large signal measurement results are presented and its performance evaluated     

Increasing the thin film inductance by using soft magnetic Co92Zr8 as conductor

Planar-type thin-film inductor has been fabricated using Co₉₂Zr₈ soft magnetic thin film with high permeability as conductor. The inductance of the Co₉₂Zr₈ inductor is about five times more than that of the Cu inductor at frequency 60 MHz. At the same time, the dissipation of thin-film inductor using Co₉₂Zr₈ is similar with that of the Cu inductor. This result presents a novel method for increasing the inductance of thin-film inductor with simple technical process.     

Compact, High-$Q$, and Low-Current Dissipation CMOS Differential Active Inductor

This letter presents an improved, compact, and tunable high-Q differential active inductor implemented in Silterra's industry standard 0.18 mum CMOS process. The improved differential active inductor demonstrates a Q ap 1000 at high frequency region. Low-current dissipation is achieved by reusing the current from the differential gyrator for stabilizer and negative impedance circuit. A replica bias circuit has been introduced to allow current-controlled inductance of the improved differential active inductor. Sensitivity of the improved differential active inductor to process variation is also included in this letter.     

Development of RF/microwave on-chip inductors using an organic micromachining process

The design and development of a micromachined spiral inductor using an organic micromachining process are presented. The process utilizes an ultra-thick negative photoresist SU-8 to elevate an inductor structure above a substrate. The micromachined inductors have been designed and fabricated on solid and hollow ground planes to, investigate the feasibility for achieving high Q-factors. The experimental results demonstrate that a micromachined inductor integrated on a Si substrate achieves a Q-factor of 19.3 at 2.1 GHz.     

Record Q symmetrical inductors for 10-GHz LC-VCOs in 0.18-/spl mu/m gate-length CMOS

We report a single-loop inductor suitable for integration in a differential voltage-controlled oscillator (LC-VCO) with 0.6-nH inductance and record quality factors of 18 at 10 GHz and 20 at 15 GHz fabricated in an industrial CMOS process on a 10 /spl Omega/cm substrate. A new lumped element model which accurately describes the inductor performance without the need for frequency-dependent elements is presented. During the course of this work, we found that a patterned ground shield significantly improves the inductor performance at these frequencies, but only when the polysilicon bars are connected from the center of the inductor.     

Fabrication and performance of a micromachined 3-D solenoid inductor

A high-Q and f_res (self-resonant frequency)solenoid inductor was fabricated by using the microelectromechanical systems(MEMS) technology with air-core structure. This inductor has an air core and an electroplated copper coil to reduce the series resistance, and the solenoid structure with laterally laid out structure saves the chip area significantly. The measurement results show that this inductor has high Q-factor and stable inductance over wide range of operating frequency. The maximum Q-factor of this inductor is 38 and the inductance is 1.78 nH at 5 GHz with an air core of 45 μm. Moreover, the Q-factor and the inductance grow with the increasing of the air core.