联合均衡和多重深度TCM译码技术研究

针对ATSC DTV系统,提出一种多重深度TCM译码作为软判决的联合均衡及译码方案,从而降低误差传播,提高了均衡器的性能.新方案仅增加了译码输出单元,复杂度较深度为1时增加并不大.当采用译码深度为1的TCM译码输出作为反馈,比硬判决反馈时的均衡器收敛门限降低了6 dB.当最大的译码深度增加到6时,均衡器收敛的门限进一步降低了3 dB,从而比硬判决时均衡器的收敛门限降低9 dB.     

MQAM T—TCM研究

本文根据Turbo编码和TCM原理,提出一种更为合理的MQAM T－TCM实现结构,这种现实方式可推广到PSK T－TCM系统,并导出与其相应的译码算法,通过计算机模拟对其性能进行了分析,证明了改进结构的正确性。     

移动卫星信道中的视频传输

为向远程便携通信提供低速率的视频服务，提出了一种基于卫星信道的级联编码系统，该系统综合运用了实时信道估计、软判决译码、TCM、深度交织和纠错编码等技术，它不仅可用于语音通信，也适用于MPEG－4标准的图像传输。     

高效数字调制技术及其DSP实现

介绍两种高效数字调制技术--FQPSK及网格编码调制(TCM)技术.FQPSK是针对高频谱效率和高功率效率要求产生的一种调制方式,分析了其调制原理并进行了DSP实现.TCM技术是一种解决通信系统有效性与可靠性的方案,简单介绍4状态8PSK TCM的基本原理,阐述基于TCM技术的Viterbi译码算法的实现过程,并对不同信噪比下的误码率进行了计算机仿真.最后提出对数字通信系统组合优化的思想.     

基于序列检测的块判决辅助Turbo均衡器

该文针对高斯分布假设条件下逐符号检测均衡器的不足,提出了一种基于序列检测的块判决辅助Turbo均衡器(Turbo-BDAE)。新算法利用译码全信息估计发送序列,提高了序列估计的可靠性,引入软判决可以降低硬判决引起的错误扩散,同时结合序列检测为均衡器输出的后验概率(APP)估计提供了更可靠的信息。仿真表明,该均衡器在保持相近复杂度的同时,进一步提升了均衡系统性能,优于逐符号LMMSE均衡器和硬反馈BDFE。     

一种串行Turbo-DFH迭代解调译码方案

该文将差分跳频(DFH)系统的频率转移过程视为一种编码,提出了一种串行Turbo-DFH迭代解调译码方案。该方案的编码器由外编码器,交织器和差分跳频转移函数串行级联组成,译码器采用串行迭代结构译码。并针对DFH系统的特点,推导了一种新的DFH系统软输入软输出算法。仿真结果表明,该解调译码方案相对传统的DFH解调算法,性能得到了明显的改善。     

LTE系统中截尾卷积码译码算法研究及仿真性能分析

在LTE的下行控制信道和广播信道中采用了截尾卷积编码方式,本文介绍了LTE系统中采用的卷积编码器以及广播信道架构,详细分析了截尾卷积码的两种常用译码算法,文章提出了一种改进循环译码算法,在基于LTE-PBCH信道链路中对各种译码算法进行仿真,仿真测试结果表明,截尾卷积码可满足LTE信道对高速率业务的要求,双回溯循环译码算法的译码性能最佳。     

低复杂度频域迭代均衡技术

迭代均衡技术是一种利用信道译码反馈提高接收机性能的关键技术,信道译码器输出译码软信息,通过译码反馈能够重建发送信号,并根据反馈信号的可靠性更新前端信道均衡器的系数。通过频域实现均衡器系数的计算,具有较低的计算复杂度。随着总体迭代次数的增加,最终迭代均衡器能够收敛,从而消除多径信道引入的符号间干扰的影响,提高接收机的可靠性。     

交织的空时分组码级联不对称网格编码调制方法

根据交织的空时分组码级联TCM编码设计标准,提出了一种空时分组码级联不对称网格编码调制(A-TCM)的优化设计方案,并得到了在空时分组码级联不对称8PSK调制的TCM情况下最优的星座图旋转角度.仿真和分析结果表明,在相同的频谱效益和译码复杂度的情况下,相比传统空时分组码级联TCM的方法,新方法可进一步提高系统性能.     

一种应用于LTE系统的Viterbi译码算法

LTE(long term evolution,长期演进)系统中采用了咬尾卷积码和Turbo码来实现前向纠错,Viterbi译码是卷积码的一种杰出的译码算法,它是一种最大似然译码方法。本文基于LTE系统中的咬尾卷积码,详细分析了几种较成熟的Viterbi译码算法,并综合现有算法,提出了一种改进算法,减小了译码计算的复杂度。仿真结果表明,改进算法在降低译码计算复杂度的同时还降低了译码误比特率,因此非常适合LTE系统的译码要求。     

Markov model aided decoding for image transmission usingsoft-decision-feedback

Soft-decision-feedback MAP decoders are developed for joint source/channel decoding (JSCD) which uses the residual redundancy in two-dimensional sources. The source redundancy is described by a second order Markov model which is made available to the receiver for row-by-row decoding, wherein the output for one row is used to aid the decoding of the next row. Performance can be improved by generalizing so as to increase the vertical depth of the decoder. This is called sheet decoding, and entails generalizing trellis decoding of one-dimensional data to trellis decoding of two-dimensional data (2-D). The proposed soft-decision-feedback sheet decoder is based on the Bahl algorithm, and it is compared to a hard-decision-feedback sheet decoder which is based on the Viterbi algorithm. The method is applied to 3-bit DPCM picture transmission over a binary symmetric channel, and it is found that the soft-decision-feedback decoder with vertical depth V performs approximately as well as the hard-decision-feedback decoder with vertical depth V+1. Because the computational requirement of the decoders depends exponentially on the vertical depth, the soft-decision-feedbark decoder offers significant reduction in complexity. For standard monochrome Lena, at a channel bit error rate of 0.05, the V=1 and V=2 soft-decision-feedback decoder JSCD gains in RSNR are 5.0 and 6.3 dB, respectively.     

Decoding of trellis-encoded signals in the presence of intersymbolinterference and noise

A novel receiver for data-transmission systems using trellis-coded modulation is investigated. It comprises a whitened-matched filter and a trellis decoder which combines the previously separated functions of equalization and trellis-coded modulation (TCM) decoding. TCM encoder, transmission channel, and whitened-matched filter are modeled by a single finite-state machine with combined intersymbol interference and code states. Using ISI-state truncation techniques and the set-partitioning principles inherent in TCM, a systematic method is then developed for reducing the state complexity of the corresponding ISI and code trellis. A modified branch metric is used for canceling those ISI terms which are not represented by the trellis states. The approach leads to a family of Viterbi decoders which offer a tradeoff between decoding complexity and performance. An adaptive version of the proposed receiver is discussed, and an efficient structure for reduced-state decoding is given. Simulation results are presented for channels with severe amplitude and phase distortion. It is shown that the proposed receiver achieves a significant gain in noise margin over a conventional receiver which uses separate linear equalization and TCM decoding     

Iterative Equalization and TCM Decoding with Refined Channel Value

In this correspondence, we present a new method for the iterative equalization and decoding of multilevel trellis coded modulation (TCM) signals over frequency selective channels. Results show that the proposed algorithm achieves better performance compared to the previous work on the MMSE filter- based turbo equalization for a non-binary coded modulation scheme. The performance gain is accomplished by utilizing the combined modulation and coding nature of TCM and passing the refined signal obtained from different paths to the TCM decoder as the channel value in addition to the a priori probabilities.     

卷积码维特比译码算法最佳反馈深度研究

卷积码可以用维特比算法作为译码算法,由于维特比译码器复杂度随着反馈深度的增长成指数倍增长,因而译码反馈深度对译码器的复杂度影响很大甚至可能无法实用,目前有些文献中仅给出了反馈深度的大致范围,但在硬件实现和性能仿真时无法确定一个具体的数值。通过在OFDM系统中运用卷积编码和维特比译码仿真分析发现,维特比译码器反馈深度为卷积码编码器存贮长度的5倍时,既可达到性能和硬件复杂度的良好折衷,又便于实际应用。     

Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding

A novel reconfigurable sequential decoder architecture based on the Fano algorithm is presented in which the constraint length, the threshold spacing, and the time-out threshold are all run time reconfigurable. To maximize decoding performance, a maximum possible backward depth (of a whole frame) is performed. This is achieved by using shift registers combined with memory to store the information of an entire visited path. A field-programmable gate array) prototype of the decoder is built and actual hardware decoding performances in terms of decoding speeds, bit error rates (BERs), and buffer overflow rates, are obtained and comparisons made. To overcome the decoding delay that is inherent in sequential decoders, a hybrid scheme, including simple block codes and cyclic redundancy check is proposed to limit the number of backward search operations that the sequential decoder has to execute. As a result, a significant reduction in decoding delay and buffer overflow rate is achieved while maintaining comparative decoding performance in terms of BER     

Nonlinear Programming Approaches to Decoding Low-Density Parity-Check Codes

We consider the decoding problem for low-density parity-check codes, and apply nonlinear programming methods. This extends previous work using linear programming (LP) to decode linear block codes. First, a multistage LP decoder based on the branch-and-bound method is proposed. This decoder makes use of the maximum-likelihood-certificate property of the LP decoder to refine the results when an error is reported. Second, we transform the original LP decoding formulation into a box-constrained quadratic programming form. Efficient linear-time parallel and serial decoding algorithms are proposed and their convergence properties are investigated. Extensive simulation studies are performed to assess the performance of the proposed decoders. It is seen that the proposed multistage LP decoder outperforms the conventional sum-product (SP) decoder considerably for low-density parity-check (LDPC) codes with short to medium block length. The proposed box-constrained quadratic programming decoder has less complexity than the SP decoder and yields much better performance for LDPC codes with regular structure.     

高速无线数传网格编码信号的简化解码算法

简单分析了网格编码信号在加性白高斯噪声(AWGN)信道中基于相位解码的维特比算法原理,并给出了一个两阶段解码算法的实现过程.该解码算法是基于接受到信号的相位信息进行解码,并带有一个简单的锁相环解决了相位模糊问题.两阶段解码算法对信号中的编码位和未编码位分别进行译码,因此增加了解码器的可移植性.该译码算法在保证译码性能的同时,明显降低了接收机的复杂度.     

An importance sampling technique for a symbol-by-symbol TCMdecoding/equalization algorithm

An importance sampling simulation technique is used to estimate the bit-error rate (BER) of a symbol-by-symbol trellis-coded modulation (TCM) decoder/equalizer proposed for digital microwave radio applications. To evaluate the performance at a BER smaller than 10^-6, we investigate a randomized bias technique previously developed by the authors. To properly select the bias vectors, the asymptotic (infinite signal-to-noise ratio) decision boundary is first determined. The simulation technique is then extended to the one-shot symbol-by-symbol TCM decoding/equalization algorithm which is equivalent to the recursive symbol-by-symbol detection algorithm of Abend and Fritchman (1970). By using this novel importance sampling technique, we can speed up the simulation and efficiently evaluate the BER performance of the TCM decoder/equalizer     

A hardware-efficient technique to implement a trellis code modulation decoder

This brief presents a new technique in implementing a very large-scale integration trellis code modulation (TCM) decoder. The technique aims to reduce hardware complexity and increase decoding throughput. The technique is introduced in the design of a Viterbi decoder. To simplify the decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a distance look-up table (DLUT). The concept of DLUT significantly reduces hardware requirements as this table eliminates the need for calculation circuitry. In addition, an output LUT (OLUT) is constructed based on the trellis diagram of the code. This table generates the decoding output using information provided by the algorithm. The use of this OLUT reduces the amount of storage requirement. The technique was used to design a 16-state, radix-4 codec for two-dimensional and four-dimensional TCM. The decoder was implemented in hardware after functional simulation. The tested ASIC has a core area of 1.1 mm/sup 2/ in 0.18-/spl mu/m CMOS. A decoding speed of 1 Gbps was achieved. Implementation results have shown that LUTs can be used to decrease hardware requirement and increase decoding speed.     

A soft-output decoding algorithm for concatenated systems

In order to fully utilize the SDD (soft-decision decoding) capacity of the outer codes in a concatenated system, reliability information on the inner decoder outputs (called soft outputs) needs to be provided to the outer decoder. This paper shows that a modified MAP algorithm can be effectively and accurately used to generate such information. In the course of the presentation, a metric based on the reliability information is proposed for the outer decoder. This metric has the Euclidean metric on AWGN channels as its special case, which leads to the concept of generalized SDD (GSDD). Several practical concerns regarding the proposed soft-output decoder are addressed through theoretical analysis and simulation: the effect of finite decoding depth, computational complexity, range overflow, and scaling. Comparisons to previous work on soft-output decoders are made