基于SATAⅡ协议的CRC32并行算法的研究

在介绍CRC校验原理和传统CRC32串行比特算法的基础上,由串行比特型算法推导出一种CRC32并行算法。并结合SATAⅡ协议的要求,完成了SATAⅡ主控制器设计中CRC生成与校验模块的设计。最后通过在ISE平台上编写Verilog硬件描述语言,对SATA协议中帧结构数据进行仿真,验证该CRC32并行算法能够满足SATA接口实时处理的要求。     

可纠正单个错误的并行CRC解码器的设计

在数据传输的过程中通常使用循环冗余校验（CRC）,以检查数据传送过程中是否发生了错误.通常当解码器发现数据帧中有错误发生时都会要求重新发送该数据帧.针对有的同步协议要求解码器同时具有纠正帧头部分发生的单个错误的功能.以CRC的基本原理为基础,分别从算法和程序实现上,介绍了一种高效的硬件实现并行8位CRC-ITU-T检查并纠正发生在16位原始数据和16位CRC码中单个传输错误的校验器.最后给出了相应的综合结果和时序仿真图.     

基于FPGA的循环冗余校验算法实现

循环冗余校验(CRC)码是数据通信中广泛应用的一种差错检测码。在介绍CRC原理的基础上,以常见的CRC-16为例,用VerilogHDL硬件描述语言设计该算法。利用Altera公司的EDA开发工具软件QuartusII6.0,给出仿真波形图以及可以共享的模块,该模块既是CRC码生成器,又是待校验数据的校验器。仿真结果表明,这是一种实现CRC算法的有效方法,其工作频率可达到420.17MHz。     

基于FPGA的SATAⅢ控制器的实现

根据SATAⅡ协议与SATAⅢ协议的不同,分别从物理层、链路层和传输层详细讨论了基于FPGA的SATAⅢ协议的实现,成功实现了控制器与支持SATAⅢ协议的SSD硬盘之间的通信。     

一种SATA Ⅲ的Sigma-Delta小数分频扩频时钟产生器设计

整数分频扩频时钟产生器具有较大的频率分辨率,不能满足SATA Ⅲ的要求,针对该问题提出了一种SATA Ⅲ的6 GHz Sigma-Delta小数分频扩频时钟产生器的设计。扩频时钟产生器基于65 nm CMOS工艺,采用了数字MASH SigmaDelta频率调制技术和一个产生33 k Hz的三角波产生器,输出频率达到6 GHz,向下扩频达到5 000 ppm。测试结果表明,在1.2 V的电源电压下,功耗为48 m W,非扩频时钟的峰峰抖动为8 ps,电磁干扰降低了15 d B。Sigma-Delta小数分频扩频时钟产生器克服了整数分频器扩频时钟产生器的缺点,较好地满足了SATA Ⅲ的要求。     

一种SATA Ⅲ失调锁相环扩频时钟产生器设计

扩频时钟产生器可以分散频率谐波的能量、减小单位带宽内的辐射能量,因此,扩频时钟产生器广泛应用在SATA Ⅲ等系统中。给出了一种基于失调锁相环技术的SATA Ⅲ扩频时钟产生器的设计方法。在扩频时钟产生器中,一个低频扩频信号和一个直接数字频率合成器进行频率合成,然后和一个高频信号混频,产生一个更高的调制参考源。扩频时钟产生器采用1.2 V 0.13μm CMOS工艺,功耗为21.16 m W,主要的频率功率减小了16 d B,芯片面积0.7*0.45 mm2。测试结果表明,采用失调锁相环技术,扩频时钟产生器具有较低的时钟抖动,较小的EMI辐射功率,较好地满足了SATA Ⅲ的需求。     

SATA3.0物理层设计与实现

SATA(Serial Advanced Technology Attachment)接口是当前大容量硬盘的常用接口之一,具有速度快、传输稳定等突出优点,因此对SATA协议的研究和物理实现引起了学术界和企业的广泛关注。通过对SATA3.0协议的应用分析,基于Xilinx Kintex-7 FPGA内置的收发器GTX,实现了SATA3.0协议的物理层设计,尤其是OOB(Out of Band)信号检测与物理层初始化状态机。通过VIVADO在线逻辑分析仪ILA等工具,对设计的逻辑进行测试,显示主机与设备之间能够通过设计的逻辑成功建立通信。     

ModBus通信协议及编程

通过现场总线技术可以实现测控设备的分散化、网络化、智能化。现场总线技术的核心是通信技术及通信协议，ModBus协议是其中之一，目前已成为一种应用于工业控制器上的标准通信协议，受到多种工业组态软件的支持。文中介绍了ModBus协议的通信格式，指出了编程要点并给出了命令列表及CRC码的生成程序。     

M0dBus通信协议及编程

通过现场总线技术可以实现测控设备的分散化、网络化、智能化.现场总线技术的核心是通信技术及通信协议,M0dBus协议是其中之一,目前已成为一种应用于工业控制器上的标准通信协议,受到多种工业组态软件的支持.文中介绍了ModBus协议的通信格式,指出了编程要点并给出了命令列表及CRC码的生成程序.     

CRC算法在ATM协议识别中的应用研究

网络协议识别技术是网络对抗领域中的一项关键技术。简要介绍了网络协议识别技术在网络对抗中的重要性,依据ATM信元结构,总结归纳了ATM协议的基本特征,详细分析了CRC搜索算法的基本原理、实现步骤和方法,基于CRC搜索算法,重点分析了2种利用HEC字节进行ATM协议识别的方法——固定边界搜索法和移动窗口搜索法,并依据协议识别过程设计了移动窗口CRC检测模块的实现框架。     

An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator

Manufacturers of MOS microprocessors have been expanding their product families to include function or task oriented LSI peripheral controllers. In the data communications area, circuits such as universal synchronous/asynchronous receiver/transmitters, bit oriented data link controllers, and multiprotocol handlers have greatly simplified systems design. This paper describes a totally unique device-the polynomial generator checker (WC) that monitors transactions on a data bus and performs functions such as programmable character comparisons, parity generation/checking, and "intelligent" block error generation/checking. An overview of character oriented data link controls and cyclic redundancy check/longitudinal redundancy check (CRC/LRC) provides an introduction to the functions and applications of the PGC. Several innovative architectural constructs be described that enable the device to fit within the die cavity of a 16 pin dual-in-like package.     

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures

This paper proposes a distributed two-rail checker architecture which is specifically targeted to self-checking bus-based systems. The architecture makes use of a single bus line to provide error indication. With respect to conventional two-rail checkers additional diagnosing capabilities are provided. The checker is totally-self-checking with respect to stuck-at faults. It features also good self-testing properties with respect to parametric faults, such as bridgings and delay faults.     

Lowering power consumption in concurrent checkers via input ordering

This paper presents an efficient and scalable technique for lowering power consumption in checkers used for concurrent error detection. The basic idea is to exploit the functional symmetry of concurrent checkers with respect to their inputs, and to order the inputs such that switching activity (and hence power consumption) in the checker is minimized. The inputs of the checker are usually driven by the outputs of the function logic and check symbol generator logic-spatial correlations between these outputs are analyzed to compute an input order that minimizes power consumption. The reduction in power consumption comes at no additional impact to area or performance and does not require any alteration to the design flow. It is shown that the number of possible input orders increases exponentially in the number of inputs to the checker. As a result, the computational cost of determining the optimum input order can be very expensive as the number of inputs to the checker increases. This paper presents a very effective technique to build a reduced cost function to solve the optimization problem to find a near optimal input order. It scales well with increasing number of inputs to the checker, and the computational costs are independent of the complexity of the checker. Experimental results demonstrate that a reduction in power consumption of 16% on the average for several types of checkers can be obtained using the proposed technique.     

一种应用于SATA硬盘的物理隔离卡的设计与实现

设计了一种双硬盘物理隔离卡的实现方案,详细介绍了基于PCI总线的物理隔离卡的隔离原理、硬件组成及控制程序的设计。该方案采用先进的物理隔离技术和网络连接控制技术,可对连网计算机的SATA硬盘信息实施有效的保护。     

总线监视器的设计

随着集成电路设计规模的不断增加，传统的验证方法学由于无法提供足够的能力来检查系统所有可能功能的正确性，已经不能满足SoC验证的需求。验证重用方法学是解决这一问题的有效途径。在SoC的验证过程中．利用总线监视器对片上总线上发生的事务进行实时监视，并将监视结果以机器可读的格式显示出来，从而可以帮助验证工程师有效地判断数据传输的正确性，达到验证单个模块和系统功能的目的。本文提出了一种SoC功能。验证平台中总线监视器的设计方法，并给出了具体的实现过程。     

CAN总线中CRC编码的硬件实现

基于CAN总线数据传输过程中加入的CRC编码技术与原理,本文首先给出了比特串行CRC编码原理及基于除法编码运算的CRC编码算法硬件实现方法。然而,为了满足高速数据传输的需要,本文进一步给出了,利用空间换取时间的比特并行CRC编码算法的详细推导过程,最后是采用VHDL语言与FPGA器件,完成了CAN总线中比特并行CRC编码算法的硬件仿真、综合、布线及下载配置,结果表明完全达到了预期的设计要求。     

Design of self-checking fully differential circuits and boards

A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The totally self-checking (TSC) goal is achieved for linear FD implementations provided that the checker CM threshold is small enough with respect to the specified margins of erroneous behavior in the circuit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/soft-fault model. A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. The circuit outputs are accepted to deviate within a 10% band. With the implemented checker, the TSC goal is not achieved for some faults in narrow regions of the frequency band. For the worst case, a hard fault which results in a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an accepted output deviation of 15%. This is, however, more demanding on the checker (which currently takes less than 3% of the total area and about 7.6% of the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the checker strongly code disjoint (SCD). This is easy to implement since an off-line test is also required for the checker. The checker outputs a double-rail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. The circuit-level mixed-signal approach is extended to the board level by means of the IEEE Std. 1149.1 digital test bus     

Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata

Complementary metal-oxide semiconductor (CMOS) technology may face so much problems in future due to the smaller size of transistors and increase in circuits’ volume and chips temperature. A new technology that can be a good alternative to CMOS circuits is quantum-dot cellular automata (QCA). These technologies have features such as a very low power consumption, high speed and small dimensions. In nano-communication system, error detection and correction in a receiver message are major factors. In addition, circuit reversibility in QCA helps designs a lot. In this research, generator and checker circuit of the reversible parity and eventually their nano-communication system are designed reversible using odd parity bit. The proposed circuits and the theoretical values are tested by QCADesigner 2.0.3 simulator to show the correct operation of the circuits. According to the simulation results, the proposed circuits compared with the previous structure improve delay by 90–75–35% in generator and checker structures of parity and their reversibility of nano-communication system, respectively. The proposed circuits are used in nano-transmitters and nano-receivers.

     

嵌入式SATA2.0接口控制器中的非对称缓冲器设计

本文描述了基于Xilinx Virtex-5FPGA的嵌入式SATA2.0主机接口控制器中,物理层与链路层之间数据位宽转换缓冲器的设计方法.针对转换过程中可能会出现的数据错序问题,采用多比特移位寄存器组设计了应用于物理层16bit与链路层32bit位宽数据之间的转换电路.仿真和板级验证结果表明,该逻辑电路与Xilinx FPGA内嵌的FIFO相比,平均时延降低了70%,在完成相同功能的情况下,使用了更少的芯片资源和控制逻辑.