180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

Analysis, Design, and $X$-Band Implementation of a Self-Biased Active Feedback $G_{m}$ -Boosted Common-Gate CMOS LNA

This paper explores the use of active feedback to boost the transconductance of a common-gate (CG) low-noise amplifier and achieve simultaneous low noise and input power match. Unlike transformer coupled topologies, the CG input stage is dc-coupled to a self-biased common-source feedback amplifier (for $g_{m}$ boosting), thus eliminating the need of external bias circuitry. Noise and intermodulation analysis with and without $g_{m}$ boosting are extensively studied yielding closed-form expressions of the noise figure (NF) and third-order input-referred intercept point (IIP3) that are useful for circuit design and optimization. A 9.6-GHz differential prototype implemented in a 0.18-$mu$ m technology using only NMOS transistors, achieves a minimum NF of 4 dB, an IIP3 of ${-}$ 11.3 dBm, a return loss of ${-}$ 17 dB, and a transducer gain of 18 dB while dissipating 10 m (excluding buffer circuit) from a 1.8-V supply voltage. The active chip area is 0.11 $mu$m $^{2}$.      

Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13-$mu$m CMOS Technology

A compact and broadband 0.8–77.5-GHz passive distributed drain mixer using standard 0.13-$mu$ m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of ${hbox{5.5}} pm {hbox{1}}$ dB from 0.8 to 77.5 GHz with a compact size of 0.67$,times,$ 0.58 mm$^{2}$ . The output 1-dB compression point is ${-}{hbox{8.5}}$ dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption.      

A 10–40 GHz Broadband Subharmonic Monolithic Mixer in 0.18 $mu$ m CMOS Technology

A 10–40 GHz broadband subharmonic monolithic passive mixer using the standard 0.18 $mu$ m CMOS process is demonstrated. The proposed mixer is composed of a two-stage Wilkinson power combiner, a short stub and a low-pass filter. Likewise, the mixer utilizes a pair of anti-parallel gate-drain-connected diodes to achieve subharmonic mixing mechanism. The two-stage Wilkinson power combiner is used to excite a radio frequency (RF) and local oscillation (LO) signals into diodes and to perform broadband operation. The low-pass filter supports an IF frequency range from dc to 2.5 GHz. This proposed configuration leads to a die size of less than 1.1$,times,$ 0.67 mm$^{2}$ . The measured results demonstrate a conversion loss of 15.6–17.6 dB, an LO-to-RF isolation better than 12 dB, a high 2LO-to-RF isolation of 51–59 dB over 10–40 GHz RF bandwidth, and a 1 dB compression power of 8 dBm.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

A Two-Port Single-Mode Fiber–Silicon Wire Waveguide Coupler Module Using Spot-Size Converters

In this paper, the performance of a two-port single-mode fiber–silicon wire waveguide coupler module which utilizes an identical spot-size converter (SSC) at the input and output ports is reported. Each of the silicon (Si)-based SSCs comprised cascaded horizontal linear and vertical nonlinear up-tapers measured 300 and 200 $mu$ m in length, respectively, in a common silicon-on-insulator (SOI) substrate. The structural parameters of the tapers were designed for compactness and relaxed tolerance to fabrication errors. The total length of the two-port coupler module was 1000 $mu$ m plus the variable length of the wire waveguide connecting the two SSCs. The mode-field diameter (MFD) of the Si-wire waveguide, 0.32$,times,$0.46 $mu$m $^{2}$, was transformed to the diameter of 2.8$,times,$ 8.0 $mu$ m$^{2}$ at the wavelength of 1.55 $mu$ m (corresponding to an area expansion of about 150 times) and vice versa by the SSCs with a net transmission loss of 4.1 dB/port. The field-mismatch loss between the SSC and the single-mode fiber with the MFD of 5.2 $mu$m was 2.1 dB/port.      

Operation of a 25-Gb/s Direct Modulation Ridge Waveguide MQW-DFB Laser up to 85 $^{circ}$ C

We demonstrated a 25-Gb/s direct modulation up to 85 $^{circ}$C with a 1.3- $mu$m InGaAlAs ridge-waveguide multiple-quantum-well distributed-feedback laser. The dependence of the relaxation oscillation frequency on current was 3.3 GHz/mA$^{1 / 2}$, and this is the highest value ever reported for 200-$mu$m-long lasers in the 1.3-$mu$m wavelength region. The $alpha$ parameter was around 2.7 at 25 $^{circ}$C, and an error-free operation after a 10-km single-mode fiber transmission was obtained up to 85 $^{circ}$C.      

Injection Locking and Switching Operations of a Novel Retro-Reflector-Cavity-Based Semiconductor Micro-Ring Laser

Injection locking and switching characteristics are investigated in the novel retro-reflector-cavitiy-based semiconductor ring laser with equivalent circular radius of 26 $mu$ m. The allowed detuning range is up to ${sim}$3 GHz wide and the highest side mode suppression ratio of ${sim}$ 43.7 dB can be achieved. A fast response speed of ${sim}$70 ps to the cavity is achieved, which indicates that this device can be utilized as an all optical switch at a data rate of 10 Gb/s or higher.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.      

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

Widely Tunable Micro-Mechanical External-Cavity Diode Laser Emitting Around 2.1 $mu$ m

A widely tunable $(Delta lambda/lambda =7hbox{%})$ micro-mechanical external cavity GaSb-based diode laser ($mu$ ECL) emitting around 2.1 $mu$ m is presented. A micro-machined grating with a rectangular grating profile, which can be tilted electrostatically, is employed as wavelength selective element within the external cavity using a Littrow configuration. An optimized grating profile leads to a high diffraction efficiency in the ${-}1$st diffraction order and therefore to a broad tuning range of 152 nm. The maximum output power of the fiber coupled $mu$ ECL system varied only moderately between 22 and 10 mW across the tuning range.      

A 16–44 GHz Compact Doubly Balanced Monolithic Ring Mixer

A novel and compact 16–44 GHz ultra-broadband doubly balanced monolithic ring mixer for Ku- to Ka-band applications implemented with a 0.15-$mu$m pHEMT process is presented. The proposed mixer is composed of a C-band miniature spiral balun and a 180$^{circ}$ hybrid formed with an interdigital coupler, a low-pass $pi$-network, and a high-pass T-network. The 180$^{circ}$ hybrid eliminates the use of a cross-over structure for application in the balanced mixer, as well as provides an output port for the RF extraction of up-converter application. This proposed configuration leads to a die size of less than 0.8$,times,$ 0.8 mm$^{2}$ . From the measured results, the mixer exhibits an 11–14 dB conversion loss, a 27–50 dB high LO-to-IF isolation over 16–44 GHz RF/LO bandwidth, and a 1-dB compression power of 14 dBm for both down- and up-converter applications.      

A 2.45/5.2 GHz Image Rejection Mixer With New Dual-Band Active Notch Filter

A 2.45/5.2 GHz dual-band Gilbert downconversion mixer with image rejection function is presented, which is implemented using the 0.18 $mu$m CMOS technology. The proposed differential dual-band image rejection circuitry is employed for the 2.45/5.2 GHz WLAN application to effectively diminish the dc power consumption and complexity of circuit design compared to the traditional Hartley or Weaver architectures. Moreover, the cross-connected pair consisted of NMOS and PMOS transistors in the proposed notch filter will further ameliorate the image rejection capability. The IC prototype achieves conversion gain of $10.5/11$ dB, IIP3 of ${-}4.9/-5.2$ dBm for ${rm RF}= 2.45/5.2$ GHz and ${rm IF}=500$ MHz while the image rejection ratio is better than 36/45 dB in the whole operation bandwidth.      

A 2.4–2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters

Low-distortion I/Q baseband filters interface with a 2.5 GHz RF receiver front-end configured as a Gm-cell in a direct-conversion architecture targeted towards WLAN 802.11b application. The active I/Q current-mode filters use AC current to carry the large swing of both desired and blocker signals, relaxing the voltage headroom requirement to a 1.2 V supply. An on chip master–slave automatic tuner is used to lock the filter bandwidth to a precision 20 MHz reference crystal oscillator, resulting in a $≪ ,$3% tuning accuracy and $≪, $ 0.5% I/Q bandwidth matching. The receiver achieves a 3.2 dB DSB NF, ${-}$14 dBm out-of-band IIP3, and ${+}$ 27 dBm worst case IIP2, all referred to the LNA input, while drawing 30mA from a 2.7 V supply. The chip is fabricated in a 0.5 $mu$m 46 GHz $f_{T}$ SiGe BiCMOS process. The active area is 2.54 mm$^{2}$ .      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 $mu$ m CMOS

A V-band frequency doubler monolithic microwave integrated circuit with a current re-use buffer amplifier is presented. The circuit is designed and fabricated using 0.13 $mu$m CMOS technology. The buffer amplifier uses a current re-use topology, which adopts series connection of two common source amplifiers for low dc power consumption. The suppression of the fundamental frequency is obtained by shunting the input frequency at the output node of the doubler and the drain nodes of two common-source stages of the buffer amplifier. The fabricated frequency doubler exhibits an output power of ${-}$4.45 dBm and a conversion gain of ${-}$ 0.45 dB at input frequency of 27.1 GHz with an input power of ${-}$4 dBm. The suppression of the fundamental signal is 49.2 dB. The total dc power dissipation is 9 mW while the buffer amplifier consumes 5 mW. The integrated circuit size including pads is 1.24 mm$, times ,$0.75 mm. To our knowledge, this is the highest suppression with low-power dissipation among V-band frequency doublers.