Experimental study on the thermo-mechanical effects of underfill and low-CTE substrate in a flip-chip device

Moiré interferometry was used to analyze the thermal deformation of four flip-chip devices mounted on FR-4 substrate and a new multi-layer substrate, with and without underfill. Thermal loading was applied by cooling the devices from 100 °C to room temperature (25 °C). The effects of underfill and the low-CTE (coefficient of thermal expansion) substrate on thermal deformation were investigated. The experimental results showed that the underfill curved in a manner similar to the silicon chip. For the flip-chip devices mounted on the multi-layer substrate, the CTE mismatch between the silicon chip and substrate was reduced, and bending deformation decreased. Of the four flip-chip devices studied, the underfilled flip-chip device mounted on the multi-layer substrate had the least deformed solder balls.     

Effect of different temperature cycling profiles on the crack initiation and propagation of Sn–3.5Ag wave soldered solder joints

Temperature cycling of a test board with different electronic components was carried out at two different temperature profiles in a single-chamber climate cabinet. The first temperature profile ranged between −55 and 100 °C and the second between 0 and 100 °C. Hole mounted components and secondary side SMD components were wave soldered with an Sn–3.5Ag alloy. Joints of both dual in line (DIL) packages and ceramic chip capacitors were investigated. Crack initiation and propagation was analysed after every 500 cycles. In total, 6500 cycles were run at both temperature profiles and the observations from each profile were compared.For both kinds of components analysed, cracks were first visible for the temperature profile ranging between −55 and 100 °C. For this temperature profile, and for DIL packages, cracks were visible already after 500 cycles, whereas for the other temperature profile, cracks initiated between 1000 and 1500 cycles. The cracks observed after 1500 cycles were visibly smaller for the temperature profile ranging between 0 and 100 °C, concluding that crack initiation and propagation was slightly slower for this temperature profile. For the chip capacitors, cracks were first visible after 2000 cycles.     

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.     

Fatigue analysis of miniaturized lead-free solder contacts based on a novel test concept

The paper presents the method of generating lifetime-prediction-laws on special prepared very stiff specimen. The combination of thin- and thick-film technology allows building up test samples on ceramic very similar to electronic packages including the measurement issues. Influences of pad surface metallurgy, microstructure of solder, ineutectic solder alloys and assembly process parameter are regarded now. The investigation objects provide monitoring of electrical and mechanical damage process of SnAgCu solder bump. Different thermo-mechanical loads will be applied in temperature ranges of 0 to +80 °C, −40 to +125 °C and −50 to +150 °C, where the temperature gradient and cycle frequency also vary. A Variation of four different chip sizes allows the determination of fatigue laws for each temperature profile, to be able to compare in between them. The results of these tests will give universal lifetime-prediction laws for SnAgCu base solder joints. Main goals are to find coefficients for lifetime prediction models such as Coffin–Manson- or Norris–Landzberg-relation, which are transferable in between different electronic packages.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.     

Pb-free high temperature solders for power device packaging

Reliabilities of joints for power semiconductor devices using a Bi-based high temperature solder has been studied. The Bi-based solder whose melting point is 270 °C were prepared by mixing of the CuAlMn particles and molten Bi to overcome the brittleness of Bi. Then, joined samples using the solder were fabricated and thermal cycling tests were examined. After almost 2000 test cycles of −40/200 °C test, neither intermetallic compounds nor cracks were observed for CTE (Coefficient of Thermal Expansion) matched sample with Cu interface. On the other hand, certain amount of intermetallic compound such as Bi₃Ni was found for a sample with Ni interface. In addition, higher reliability of this solder than Sn-Cu solder was obtained after −40/250 °C test. Furthermore, an example power module structure using double high temperature solder layers was proposed.     

Effect of microwave preheating on the bonding performance of flip chip on flex joint

A microwave (MW) preheating mechanism of anisotropic conductive adhesive film (ACF) has been introduced in order to reduce the bonding temperature for flip chip technology. Thermal curing of epoxy shows a very sluggish and non-uniform curing kinetics at the beginning of the curing reaction, but the rate increases with time and hence requires higher temperature. On the other hand MW radiation has the advantage of uniform heating rate during the cycle. In view of this, MW preheating (for 2/3 s) of ACF prior to final bonding has been applied to examine the electrical and mechanical performance of the bond. Low MW power has been used (80 and 240 W) to study the effect of the MW preheating. It has been found that 170 °C can be used for flip chip bonding instead of 180 °C (standard temperature for flip chip bonding) for MW preheating time and power used in this study. The contact resistance (0.015–0.025 Ω) is low in these samples where the standard resistance is 0.017 Ω (bonded at 180 °C without prior MW preheating). The shear forces at breakage were satisfactory (152–176 N) for the samples bonded at 170 °C with MW preheating, which is very close and even higher than the standard sample (173.3 N). For MW preheating time of 2 s, final bonding at 160 °C can also be used because of its low contact resistance (0.022–0.032 Ω), but the bond strength (137.3–145 N) is somewhat inferior to the standard one.     

Effects of TMF heating rates on damage accumulation and resultant mechanical behavior of Sn–Ag based solder joints

Solder joint reliability depends on several service parameters such as temperature extremes encountered, dwell times at these temperatures, and the ramp-rates representing the rate at which the temperature changes are imposed. TMF of Sn–Ag based solder alloy joints of realistic dimensions were carried out with dwell of 115 min and 20 min at 150 °C and −15 °C, respectively. Different heating rates were obtained by controlling the power input during heating part of TMF cycles. Surface damage and residual mechanical strength of these solder joints were characterized after 0, 250, 500, and 1000 TMF cycles to evaluate the role of TMF heating rate on the solder joint integrity.     

Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organic substrate application

The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies were studied. As the bonding temperature decreased, the composite properties of ACF, such as water absorption, glass transition temperature (T_g), elastic modulus (E′) and coefficient of thermal expansion (α), were improved. These results were due to the difference in network structures of cured ACFs which were fully cured at different temperatures. From small angle X-ray scattering (SAXS) test result, ACFs cured at lower temperature, had denser network structures. The reliability performances of flip chip on organic substrate assemblies using ACFs were also investigated as a function of bonding temperatures. The results in thermal cycling test (−55 °C/+150 °C, 1000 cycles) and PCT (121 °C, 100% RH, 96 h) showed that the lower bonding temperature resulted in better reliability of the flip chip interconnects using ACFs. Therefore, the composite properties of cured ACF and reliability of flip chip on organic substrate assemblies using ACFs were strongly affected by the bonding temperature.     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

Rapid thermal magnetic annealing as an emerging technology in field-annealing of thin magnetic films for recording heads

An emerging field where rapid thermal processing (RTP) is now rapidly finding its first acceptance is in the industrial manufacturing of thin-film head devices for magnetic recording. Here soft-magnetic thin-film flux guide structures (usually composed of high-moment alloys containing iron, etc.) are applied onto ceramic substrate wafers (such as Al₂O₃–TiC) of sizes up to 150 mm and subsequently ‘activated' by heating and cooling in a magnetic field.We assessed the advantages of rapid thermal magnetic annealing (RTMA) in a new prototype reactor with an external electromagnet, capable of generating an extremely homogeneous magnetic field of 660 Oe (52.8 kA/m) with field lines parallel across the entire wafer area (150 mm in diameter). Samples with 1 μm thick amorphous iron-alloy layers (Fe₇₇Nb₁₁N₁₀Si₂) sputter-deposited onto ceramic substrates of single-crystalline GGG-garnet (Gd₃Ga₅O₁₂) were conventionally annealed and RTMA-annealed in N₂/H₂ at temperatures between 550 and 700°C. Structural analysis by transmission electron microscopy (TEM) and electron diffraction showed that the enhanced performance of the RTMA-annealed layers is due to the different nanocrystallization kinetics induced by the fast heating and cooling rates of RTMA.The ceramic substrate materials normally used in head manufacturing (such as Al₂O₃–TiC) have favorable grey-body properties with high emissivity (≥0.7) over a wide range of temperatures (25–700°C) and wavelengths (1.5–10 μm), which excludes the difficulties encountered in pyrometric temperature control of infrared-transparent substrates such as silicon. We conclude that RTMA yields superior soft-magnetic materials, where throughput numbers of ≥30 wafers/h are possible.     

Reliability of wire-bonding and solder joint for high temperature operation of power semiconductor device

Thick Al wires bonded on chips of power semiconductor devices were examined for thermal cycle tests, then the bonded joints were cut using microtome method, after that those were observed by scanning electron microscope and analyzed by electron back scattered diffraction. Some cracks were observed between Al wires and the chips, unexpectedly the crack lengths were almost constant for −40/150 °C, −40/200 °C and −40/250 °C tests. It is considered that re-crystallization has been progressed during the high temperature side of the thermal cycle tests.Furthermore, joint samples were prepared using high temperature solders such as Zn–Al and Bi with CuAlMn, Direct Bonded Copper insulated substrates and Mo heatsinks. The fabricated samples were evaluated by scanning acoustic microscope before and after thermal cycle tests. Consequently, almost neither serious damages nor delaminations were observed for −40/200 °C and −40/250 °C tests.     

Solder joint reliability evaluation of chip scale package using a modified Coffin–Manson equation

Thermal cycle tests were performed for chip scale package (CSP) solder joints with Sn–37mass%Pb under several thermal cycle conditions. Under the conventional thermal cycle conditions, which heat up to approximately 100 °C, microstructure coarsening occurred and solder joints were fractured. The thermal fatigue lives followed the modified Coffin–Manson equation. The exponential factors m and n, and the activation energy Q in that equation were evaluated as 0.33, −1.9 and 15.5 kJ/mol, respectively. When the maximum temperature is room temperature and the temperature range is very narrow, the solder joint fracture occurred without microstructure coarsening, and the thermal fatigue life does not follow the modified Coffin–Manson equation.     

Degradation behavior of 600 V–200 A IGBT modules under power cycling and high temperature environment conditions

One challenge for automotive hybrid traction application is the use of high power IGBT modules that can withstand high ambient temperatures, from 90 °C to 120 °C, for reliability purpose. The paper presents ageing tests of 600 V–200 A IGBT modules subjected to power cycling with 60 °C junction temperature swings at 90 °C ambient temperature. Failure modes are described and obtained results on the module characteristics are detailed. Especially, physical degradations are described not only at the package level, like solder attach delaminations, but also at the chip level, with a shift on electrical characteristics such as threshold voltage. Finally, numerical investigations are performed in order to assess the thermal and thermo-mechanical constraints on silicon dies during power cycling and also to estimate the effect of ambient temperature on the mechanical stresses.     

Wire-bond failure mechanisms in plastic encapsulated microcircuits and ceramic hybrids at high temperatures

Ceramic hybrids are the preferred solution when long-term high-temperature reliability is required, but standard plastic encapsulated microcircuits (PEMs) are an interesting alternative due to low price and high availability. Test vehicles with standard PEMs were subjected to thermal ageing at 150–175 °C. Six of eight vehicles failed after only three weeks at 175 °C, and the cause of failure was found to be microcracking at the interface between gold ball and aluminium bond pad giving rise to resistance increase. The intermetallic region was formed during high-temperature lead soldering and continued to develop during thermal ageing. The high-temperature performance of aluminium wire bonding to a selection of thick film metallizations on ceramic substrate was also investigated. Gold–palladium has previously been reported as a high-temperature solution, but we found that the mechanical strength of aluminium to gold–palladium (AuPd) degraded seriously at temperatures above 200 °C due to intermetallic formation. Aluminium to silver thick film plated with copper and nickel showed good mechanical strength and unaltered electrical resistance after four weeks thermal ageing at 250 °C.     

Electromigration of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite flip–chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

We examine electromigration fatigue reliability and morphological patterns of Sn–37Pb and Sn–3Ag–1.5Cu/Sn–3Ag–0.5Cu composite solder bumps in a flip–chip package assembly with Ti/Ni(V)/Cu UBM. The flip–chip test vehicle was subjected to test conditions of five combinations of applied electric currents and ambient temperatures, namely, 0.4 A/150 °C, 0.5 A/150 °C, 0.6 A/125 °C, 0.6 A/135 °C, and 0.6 A/150 °C. The electrothermal coupling analysis was employed to investigate the current crowding effect and maximum temperature in the solder bump in order to correlate with the experimental electromigration reliability using the Black’s equation as a reliability model. From available electromigration reliability models, we also present a comparison between fatigue lives of Sn–37Pb solder bumps with Ti/Ni(V)/Cu and those with Al/Ni(V)/Cu UBM under different current stressing conditions.     

Properties of low temperature Sn–Ag–Bi–In solder systems

The metallurgical and mechanical properties of Sn–3.5 wt%Ag–0.5 wt%Bi–xwt%In (x = 0–16) alloys and of their joints during 85 °C/85% relative humidity (RH) exposure and heat cycle test (−40–125 °C) were evaluated by microstructure observation, high temperature X-ray diffraction analysis, shear and peeling tests. The exposure of Sn–Ag–Bi–In joints to 85 °C/85%RH for up to 1000 h promotes In–O formation along the free surfaces of the solder fillets. The 85°C/85%RH exposure, however, does not influence the joint strength for 1000 h. Comparing with Sn–Zn–Bi solders, Sn–Ag–Bi–In solders are much stable against moisture, i.e. even at 85 °C/85%RH. Sn–Ag–Bi–In alloys with middle In content show severe deformation under a heat cycles between −40 °C and 125 °C after 2500 cycles, due to the phase transformation from β-Sn to β-Sn + γ-InSn₄ or γ-InSn₄ at 125 °C. Even though such deformation, high joint strength can be maintained for 1000 heat cycles.     

Impact of board and component metallizations on microstructure and reliability of lead-free solder joints

Aging and accelerated thermal cycling (ATC) have been performed on 2512 chip resistors assembled with Sn3.8Ag0.7Cu (wt.%) solder. The boards were finished with immersion Ag (IAg), electroless nickel/immersion gold (ENIG), and hot air solder leveling Sn–Pb eutectic solder (HASL), and the components’ terminations were finished with 100% Sn and Sn8.0Pb (wt.%). The boards were reflowed with an average cooling rate of 1.6 °C/s. It was found that the microstructure and reliability of the solder joints depended on the board surface finish. The boards containing small amounts of Pb (from board/component terminations) were the most reliable. Solder joints to copper showed a significantly higher number of cycles to first failure than the joints on nickel. Better reliability of the Sn3.8Ag0.7Cu/Cu joints was attributed to an increased copper content in the bulk due to substrate dissolution.     

Reliability study of the electroless Ni–P layer against solder alloy

Copper (Cu) has been widely used in the under bump metallurgy of chip and substrate metallization for chip packaging. However, due to the rapid formation of Cu–Sn intermetallic compound (IMC) at the tin-based solder/Cu interface during solder reaction, the reliability of this type of solder joint is a serious concern. In this work, electroless nickel–phosphorous (Ni–P) layer was deposited on the Cu pad of the flexible substrate as a diffusion barrier between Cu and the solder materials. The deposition was carried out in a commercial acidic sodium hypophosphite bath at 85 °C for different pH values. It was found that for the same deposition time period, higher pH bath composition (mild acidic) yields thicker Ni–P layer with lower phosphorous content. Solder balls having composition 62%Sn–36%Pb–2%Ag were reflowed at 240 °C for 1 to 180 min on three types of electroless Ni–P layers deposited at the pH value of 4, 4.8 and 6, respectively. Thermal stability of the electroless Ni–P barrier layer against the Sn–36%Pb–2%Ag solder reflowed for different time periods was examined by scanning electron microscopy equipped with energy dispersed X-ray. Solder ball shear test was performed in order to find out the relationship between the mechanical strength of solder joints and the characteristics of the electroless Ni–P layer deposited.The layer deposited in the pH 4 acidic bath showed the weak barrier against reflow soldering whereas layer deposited in pH 6 acidic bath showed better barrier against reflow soldering. Mechanical strength of the joints were deteriorated quickly in the layer deposited at pH 4 acidic bath, which was found to be thin and has a high phosphorous content. From the cross-sectional studies and fracture surface analyses, it was found that the appearance of the dark crystalline phosphorous-rich Ni layer weakened the interface and hence lower solder ball shear strength. Ni–Sn IMC formed at the interfaces was found to be more stable at the low phosphorous content (14 at.%) layer. Electroless Ni–P deposited at mild acidic bath resulting phosphorous content of around 14 at.% is suggested as the best barrier layer for Sn–36%Pb–2%Ag solder.