Ka-band InP high electron mobility transistor monolithic microwave integrated circuit reliability

The reliability of AlInAs/GaInAs high electron mobility transistor (HEMT) monolithic microwave integrated circuits on InP substrates from HRL Labs has been studied with elevated-temperature lifetests on Ka-band LNAs, as well as ramped-voltage tests on individual capacitors. In the lifetests the LNAs were put under normal DC bias, and aging was accelerated by heating to channel temperatures of 190°C and 210°C. Room-temperature characterizations involved DC tests of HEMT parameters as well as 30 GHz measurements of gain, noise figure and phase. Aging caused the noise figure to drop by a few tenths of a dB, and the phase changed by ±10°. The gain dropped gradually by several dB. Taking 1 dB drop in gain as the failure criterion, we find an activation energy of 1.1 eV, and a mean time to failure (MTTF) at an operating channel temperature of 70°C of 7×10⁶ h. In the ramped-voltage tests, 10×10 μm² capacitors were taken to breakdown at two different temperatures, and several ramp rates. This yielded a voltage acceleration factor of γ=36–39 nm/V, and thermal activation energy of 0.11–0.13 eV. Next, ramped voltage tests were conducted on 200×200 μm² capacitors, typical of those in circuits. These were done at 25°C and 3.0 V/s only, and at least 1000 specimens were tested per wafer. The known acceleration factors were used to find the MTTFs at 70°C, with operating biases of 5 or 10 V. For the majority of the population the MTTFs are about 10⁹ h, while only 0.07% of the population has MTTF less than 1×10⁶ h. The combination of results from elevated-temperature lifetests and ramped-voltage capacitor tests indicates excellent reliability for this MMIC technology in terms of known “wearout” failure mechanisms.     

Hydrogen incorporation, diffusivity and evolution in bulk ZnO

Hydrogen is readily incorporated into bulk, single-crystal ZnO during exposure to plasmas at moderate (100–300°C) temperatures. Incorporation depths of >25 μm were obtained in 0.5 h at 300°C, producing a diffusivity of 8 × 10⁻¹⁰ cm²/V s at this temperature. The activation energy for diffusion is 0.17 ± 0.12 eV, indicating an interstitial mechanism. Subsequent annealing at 500–600 °C is sufficient to evolve all of the hydrogen out of the ZnO, at least to the sensitivity of Secondary Ion Mass Spectrometry (<5 × 10¹⁵ cm⁻³). The thermal stability of hydrogen retention is slightly greater when the hydrogen is incorporated by direct implantation relative to plasma exposure, due to trapping at residual damage.     

Influence of rapid thermal annealing on morphological and electrical properties of RF sputtered AlN films

Aluminum nitride films were deposited, at 200 °C, on silicon substrates by RF sputtering. Effects of rapid thermal annealing on these films, at temperatures ranging from 400 to 1000 °C, have been studied. Fourier transform infrared spectroscopy (FTIR) revealed that the characteristic absorption band of Al–N, around 684 cm⁻¹, became prominent with increased annealing temperature. X-ray diffraction (XRD) patterns exhibited a better, c-axis, (0 0 2) oriented AlN films at 800 °C. Significant rise in surface roughness, from 2.1 to 3.68 nm, was observed as annealing temperatures increased. Apart from these observations, micro-cracks were observed at 1000 °C. Insulator charge density increased from 2×10¹¹ to 7.7×10¹¹ cm⁻² at higher temperatures, whereas, the interface charge density was found minimum, 3.2×10¹¹ eV⁻¹cm⁻², at 600 °C.     

Reliability results of HBTs with an InGaP emitter

Accelerated lifetest results are presented on HBTs with InGaP emitters. An Arrhenius plot indicates the existence of a temperature dependent activation energy, E_a. A low E_a mechanism dominates above T_j 380 °C and a high E_a mechanism dominates at lower temperature. The critical transition temperature between regimes is determined using the method of maximum likelihood. The difference in E_a’s between low and high temperature regimes is statistically significant.A comparison is made between lifetimes determined from at temperature vs. 40 °C data. No significant difference is observed indicating that beta degradation can be monitored at temperature only and cooling to low temperature is not necessary. Other comparisons indicate that junction temperatures up to 367 °C can still provide good estimates of lower temperature behavior.By the method of maximum likelihood, the predicted MTTF at T_j = 125 °C is 7.6 × 10⁹ h with 95% CBs of [6.4 × 10⁸, 8.9 × 10¹⁰]. Given the typical industry standard of 1 × 10⁶ h, the reliability requirements are easily met.It is suggested that the standard of 1 × 10⁶ h does not adequately capture failure time variation and that a better specification is in terms of fails in time (FITs). The 10 year average FIT rate at 125 °C is found to be negligible. Assuming a much higher junction temperature of 210 °C, the average failure rate climbs to 5 FITs with an upper 95% confidence bound of 40 FITs.     

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm² capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d_eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d_eff, while d_eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10⁷ h, and the distribution becomes insignificant below 2 × 10⁶ h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.     

Threshold voltage shift in 0.1 μm self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs

Bias-temperature stress examinations of self-aligned 0.1 μm length gate GaAs MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lower doping concentration, the increase in threshold voltage in FETs was faster and a 100 mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200°C. The recovery of the performance under reverse-biased stresses was observed. The degradation is released by increasing Si doping concentration and thus we obtained the prediction of a median life exceeding 10⁶ h at 100°C by setting the Si dose of 4 × 10¹³ cm⁻², which is as high as it can be set without causing serious reduction of breakdown voltage.     

High temperature transport kinetics in heteroepitaxial LaFeO3 thin films

Heteroepitaxial LaFeO₃(1 1 0) thin films with a thickness of 150 nm were grown on LaAlO₃(0 0 1) by reactive sputtering in an inverted cylindrical magnetron geometry. Equilibrium conductivity was measured as a function of partial pressure of oxygen at T=1000 °C, and logσ plotted vs. logP(O₂) showed a minimum in conductivity for P(O₂)=10⁻¹¹ atm and a linear response between 10⁻¹⁰ and 1 atm. This linear response makes thin films of LaFeO₃ a promising material for oxygen sensor applications. We have also measured the time response of the film conductivity upon an abrupt change in the partial pressure of ambient oxygen from 10⁻² to 10⁻³ atm, which was determined at 60 s for T=700 °C and <3.5 s at T=1000 °C.     

Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: effect of ramp-up rate

Ultra-shallow p-type junction formation has been investigated using 1050°C spike anneals in lamp-based and hot-walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up to temperature with only a fraction of a second soak-time at temperature. The effects of the ramp-up rate during a spike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 155°C/s in a lamp-based RTP, and for 50 and 85°C/s in a hot-walled RTP. B⁺ implants of 0.5, 2 and 5 keV at doses of 2×10¹⁴ and 2×10¹⁵ cm⁻² were annealed. A significant reduction in junction depth was observed at the highest ramp-up rate for the shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but only when used in combination with spike anneals and the lowest energy implants.     

Degradation mechanism of GaAs MESFETs

The reliability of the Au/Pt/Ti Schottky gate of low-high doped GaAs MESFETs has been investigated by thermal step stress and accelerated life tests and their degradation mechanisms were analyzed by means of Auger electron spectroscopy, X-ray diffractometry, cross-sectional transmission electron microscopy, current-voltage, and capacitance-voltage measurements. Electrical measurements showed that the failure of the GaAs MESFETs was mainly due to the degradation of the Au/Pt/Ti/GaAs Schottky contact. An activation energy of 1.3 eV and a lifetime of 2 × 10⁸ h at 125°C for Schottky contact were evaluated. At a temperature lower than 350°C, the degradation of the Schottky contact is attributed to the decrease of net electron concentration caused by outdiffusion of host Ga atoms of GaAs. The activation energy for the decrease of net electron concentration is determined to be 1.4 eV using the capacitance-voltage measurement, which is consistent with 1.3 eV obtained by the accelerated life tests. This suggests that the major thermal degradation mechanism at a temperature lower than 350°C is the outdiffusion of Ga atoms from the channel. Meanwhile, the effective channel thickness at a temperature higher than 350°C is reduced by the formation of TiAs at the Schottky interface, the activation energy of which is determined to be 1.74 eV.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

Growth and physical properties of in situ phosphorus-doped RTLPCVD polycrystalline silicon thin films

In situ phosphorus-doped (P-doped) polysilicon (poly-Si) thin films are obtained by rapid thermal low pressure chemical vapor deposition (RTLPCVD) in a single chamber RTP machine by using diluted silane (SiH₄/Ar=10%) and phosphine (PH₃=200 ppm). Deposition kinetics of poly-Si films were studied in the 600–850°C temperature range at fixed total pressure of 2 mbar and gas flow rate (100 sccm). Activation energy of 1.82 eV was calculated in the surface reaction deposition regime. Dopant activation has been obtained sequentially by RTO at 1000°C in pure O₂ atmosphere. This later process permits to both activate the phosphorus dopant and forms an ultrathin polyoxide which blocks dopant outdiffusion. Secondary ion-mass spectrometry (SIMS) analysis showed flat P-dopant profiles throughout the film thickness with a P concentration varying from 5.5×10²⁰ to 2.4×10¹⁹ at/cm³ when the deposition temperature increases in the 600–850°C range. Grazing incidence X-ray diffraction (XRD) has been used to study the structural properties of the poly-Si layers. It appeared particularly that the amorphous to crystalline temperature transition occurs at around 650°C. Finally, four-point probe measurements showed that sheet resitivities in the mΩ cm range can be routinely achieved for in situ P-doped RTLPCVD poly-Si films.     

Investigation of Au/Ti/Al ohmic contact to N-type 4H–SiC

In this study, investigation on Au/Ti/Al ohmic contact to n-type 4H–SiC and its thermal stability are reported. Specific contact resistances (SCRs) in the range of 10⁻⁴–10⁻⁶ Ω cm², and the best SCR as low as 2.8 × 10⁻⁶ Ω cm² has been generally achieved after rapid thermal annealing in Ar for 5 min at 800 °C and above. About 1–2 order(s) of magnitude improvement in SCR as compared to those Al/Ti series ohmic systems in n-SiC reported in literature is obtained. XRD analysis shows that the low resistance contact would be attributed to the formation of titanium silicides (TiSi₂ and TiSi) and Ti₃SiC₂ at the metal/n-SiC interface after thermal annealing. The Au/Ti/Al ohmic contact is thermally stable during thermal aging treatment in Ar at temperature in the 100–500 °C range for 20 h.     

ICP dry etching of ZnO and effects of hydrogen

Two different plasma chemistries for etching ZnO were examined. Both Cl₂/Ar and CH₄/H₂/Ar produced etch rates which increased linearly with rf power, reaching values of 1200 Å/min for Cl₂/Ar and 3000 Å/min for CH₄/H₂/Ar. The evolution of surface morphology, surface composition, and PL intensity as a function of energy during etching were monitored. The effect of H in ZnO was studied using direct implantation at doses of 10¹⁵–10¹⁶ cm⁻², followed by annealing at 500–700 °C. The hydrogen shows significant outdiffusion at 500 °C and is below the detection limits of SIMS after 700 °C anneals. SEM of the etched features showed anisotropic sidewalls, indicative of an ion-driven etch mechanism.     

Comparison of p–n junction formed by BF2 and B implantation in silicon microstrip detector with low and high thermal budget: impact of fluorine on electrical characteristics

The influence of crystal damage on the electrical properties and the doping profile of the implanted p⁺–n junction has been studied at different annealing temperatures using process simulator TMA-SUPREM4. This was done by carrying out two different implantations; one with implantation dose of 10¹⁵ BF₂⁺ ions/cm² at an energy of 80 keV and other with 10¹⁵ B⁺ ions/cm² at 17.93 keV. Substrate orientation 1 1 1 of phosphorus-doped n-type Si wafers of resistivity 4 kΩ cm and tilt 7° was used, and isochronally annealing was performed in N₂ ambient for 180 min in temperature range between 400°C and 1350°C. The diode properties were analysed in terms of junction depth, sheet resistance. It has been found that for low thermal budget annealing, boron diffusion depth is insensitive to the variation in annealing temperature for BF₂⁺-implanted devices, whereas, boron diffusion depth increases continuously for B⁺-implanted devices. In BF₂⁺-implanted devices, fluorine diffusion improves the breakdown voltage of the silicon microstrip detector for annealing temperature upto 900°C.For high thermal budget annealing, it has been shown that the electrical characteristics of BF₂⁺-implanted devices is similar to that obtained in B⁺-implanted devices.     

Ultra high temperature rapid thermal annealing of GaN

All of the major acceptor (Mg, C, Be) and donor (Si, S, Se and Te) dopants have been implanted into GaN films grown on Al₂O₃ substrates. Annealing was performed at 1100–1500°C, using AlN encapsulation. Activation percentages of ≥90% were obtained for Si⁺ implantation annealed at 1400°C, while higher temperatures led to a decrease in both carrier concentration and electron mobility. No measurable redistribution of any of the implanted dopants was observed at 1450°C.     

Investigation of the influence of thermal treatment on interconnect-barrier interfaces in copper metallization systems

In this paper, we present recent results dealing with the influence of a high temperature anneal on the Cu–Ta interface in copper metallization systems. The electromigration lifetime data show a strong dependency of the electromigration robustness on the temperature budget. A bimodal behavior was observed after annealing the metallization at temperatures of 470 °C and above for more than 10 h. Surprisingly the high temperature anneal produces a late failure mode in electromigration lifetime tests resulting in a 10 times higher MTTF. To understand the influence of temperature pretreatment on electromigration behavior, TEM and SIMS have been performed on untreated samples (as fabricated) and on samples stored at 500 °C for 10 h. The TEM investigation shows no significant change in Cu grain size due to the high temperature. The Tof-SIMS investigations show that Ta diffuses into the Cu interconnect at the high temperature. A diffusion length for Ta of about 150 nm was observed for samples stored at 500 °C for 10 h. This effect has a strong impact on the results of the electromigration tests, done on lines after high temperature anneal.     

Strain relaxation in SiGe due to process induced defects and their subsequent annealing behavior

Ion implantation and reactive ion etching are known to create defects in silicon which get cured during subsequent annealing operations. In this paper we have reported the annealing behavior of phosphorus implanted into strained SiGe layer at room temperature. The implantation was performed at 155 KeV with a dose of 1×10¹⁴/cm². Post implantation annealing was performed at 600, 700, 800 and 900°C for 10 s in a rapid thermal process furnace. Annealing behavior of defects generated as a consequence of dry etching is also reported. RTP annealing on reactive ion etching (RIE) etched samples were performed at 650, 700, 750 and 800 °C. I–V, C–V and DLTS measurements hint towards the presence of permanent dislocation loops created as a consequence of RIE and implantation causing strain relaxation.