1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments.     

Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.     

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography

We have fabricated MOSFET's with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at all levels with the negative resist GMC in a tri-level configuration. Heat treatments have been as short as possible to preserve very shallow source-drain junction depths (<0.1µm). We observe quasi-long channel behavior for low bias voltages. Measured values for the transconductance are among the highest ever reported. For a channel lengthL = 0.14µm, we obtaing_{m} = 180mS/mm for a gate oxide thickness of 160Å.     

A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n⁺and p⁺regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.     

Hot-electron currents in very short channel MOSFET's

The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be Te= 9.05 × 10^-3E.     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.     

Low-power high-speed InP MISFET direct-coupled FET logic

High-dynamic-range n-channel InP MISFET direct-coupled FET logic ring oscillator and inverter integrated circuits with minimum observed propagation delay per staget_{pd} = 62ps with associated power delay product of 41 fJ and minimum observed power delay productPt_{pd} = 22fJ with associated delay of 84 ps have been fabricated on Fe-doped semi-insulating substrate material using ion implantation for contact and load channel regions and pyrolytic SiO2as the gate insulator. Accumulation-type enhancement-mode MISFET structures with source-drain separations of 1.5 µm and gate metallization lengths of 3.0 µm were employed as driver devices while both MESFET's and 1.5-µm-length ungated "velocity saturation" structures were used as loads. WithV_{DD} = 4.5V representative inverter structures exhibited logic swings of 3.58 V, noise margins of 1.00 and 0.92 V, and dc gain in the linear region of 2.2.     

Possible ballistic effects in GaAs current limiters

Two-terminal N+NN+ current limiters have been fabricated in GaAs by selective ion-implantation of the N+ and N regions into undoped substrate material. Voltage-current characteristics have been measured at 77°K, 300°K and 400°K and reveal current limiting properties above about 0.8 to 1.0 volts at all three temperatures. In the voltage range below 0.7 volts a relation of I ~ V^{3/2}was observed for the devices operating at 77°K. Such a variation has been suggested as being indicative of ballistic motion of electrons when taking into consideration that the distance between the N+ regions is in the range of 0.5 to 0.8µm and the doping concentration of the N region is about 10¹⁶cm^-3.     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

High-transconductance p-channel modulation-doped AlGaAs/GaAs heterostructure FET's

p-channel modulation-doped AlGaAs-GaAs heterostructure FET's (p-HFET's) employing two-dimensional hole gas (2DHG) were fabricated under various geometrical device parameter conditions. The p-HFET characteristics were measured at 300 and 77 K for the following three device-parameter ranges: the gate length Lg(1-320 µm), the gate-source distance Lgs(0.5-5 µm), and the layer thickness dt(35-58 nm) of AlGaAs beneath the gate. Based on the obtained results, a high-performance enhancement-mode p-HFET was fabricated with the following parameters:L_{g} = 1µm,L_{gs} = 0.5µm, andd_{t} = 35nm. The achieved extrinsic transconductance gmwas 75 mS . mm^-1at 77 K. This experimental result indicates that a gmgreater than 200 mS . mm^-1at 77 K Can be obtained in 1-µm gate p-HFET devices.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Design and performance of "1.25-µm" CMOS for digital applications

This paper presents a detailed approach for the design and performance analysis of 1.25-µm CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-µm CMOS technology, based, in part, on a set of achievable lithographic feature sizes and alignment tolerances together with a set of reasonable process geometric parameters. The process baseline is TWIN-WELL CMOS using n^-epi on an n⁺substrate as the host starting material. Two of the key geometric parameters defined are effective channel length, Le= 1 µm, and gate oxide thickness, tox= 250 Å. Other dimensions have been selected using quasi-scaling rules consistent with a 2λ of 1.25 µm. The design process starts with the selection of the average "well" doping levels from a consideration of some key short-channel effects: simple charge sharing and drain-induced barrier lowering (DIBL). The selection of a suitable operating voltage, VDD, is considered during this process as it effects junction breakdown voltage, gate oxide fields, and more importantly, potential hot-electron injection. Additional process design analyses are presented with respect to the establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed for a basic inverter structure which yields results close to those obtained through more detailed SPICE simulations. A unit delay (single fan-out) analysis is performed yielding delays of 214 ps for a VDDof 5 V and 270 ps for a VDDof 3.3 V.     

101-Stage 2 µm gate ring oscillators in laser-grown silicon islands embedded in SiO2

E/D MOS test transistors and 101-stage 2 µm gate E/D MOS ring oscillators were fabricated in laser-grown single- and multicrystal islands embedded in oxide substrates. Most transistors showed goodI-Vcharacteristics, short-channel effects, and kink effects. Ring oscillators had a switching delay per stage (τPd) of 0.4 ns and a power-delay product (τ_{Pd} middot P_{d}) of 2.5 PJ at a supply voltage (VDD) of 10-15 V. It was noted that different crystal orientations of the islands posed no difficulty in processing and VTcontrol when applied to short channel devices, and that enhanced boundary diffusion results in occasional malfunctional transistors and erroneous high surface electron mobilities (µse).     

High-voltage management in single-supply CHE NOR-type flash memories

In a flash memory, a number of voltage levels different from V/sub DD/ are needed to perform the required operations (read, program, and erase) on the array cells. In the case of single-supply memory devices, voltages higher than V/sub DD/ as well as negative voltages, which are referred to as high voltages (HVs), must be produced on-chip. This paper aims at giving the reader an overview of how HVs are generated and managed in single-supply NOR-type flash memories programmed by channel hot-electron injection. Both schemes used for conventional (i.e., bilevel) memory devices and schemes designed to meet multilevel memory requirements are addressed.     

Scaling issues related to high field phenomena in submicrometer MOSFET's

Both enhancement and depletion n-channel MOS devices with electrical channel lengths between 1 and 0.3 µm are characterized in terms of carrier heating effects. The effect of gate oxide thickness on the two-dimensional (2-D) electric field distribution has been analyzed through 2-D numerical device simulation, and its impact on carrier heating process has been experimentally quantified. Our results allow some conclusions for reduced supply voltages (2 and 3 V for temperatures of 77 and 300 K, respectively) for future NMOS technologies with design rules of 0.75 µm.     

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

Two-dimensional dynamic analysis of short-channel thin-film MOS transistors using a minicomputer

A computer program is described for simulating two-dimensional thin-film MOS transistors on a minicomputer. Data are presented showing the variation of internal carrier density with time until a steady-state condition is reached. These data show the formation of a drain-induced back channel whose conduction properties depend on the back-channel length and carrier mobility. For channel length below 2.0 µm, the two-dimensional steady-state drain current is shown to fit the expressionI_{D}/W = frac{micro_{0}C_{0}}{L[1+(micro_{0}/upsilon_{s} V_{D}{L})^{2}]^{1/2}}(V_{G} - V_{T} - V_{D/2})V{D}for values of drain voltage below a specific saturation value (V_{DM}); andI_{D}/W = frac{10^{-8)(V_{G} - V_{T})^{1/2}}{(T_{ox})^{1/2}L}.(V_{D} - V_{DM}) + I_{DM}for drain voltages above the saturation value.     

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

The LDD structure, where narrow, self-aligned n^-regions are introduced between the channel and the n⁺source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n^-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n^-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

Dependence of channel electric field on device scaling

It has been shown previously that the maximum channel electric field Emin a MOSFET is the most important parameter relating to all hot-electron effects and that Emcan be represented as (V_{DS} - V_{DSAT})/l, wherelmay be regarded as the effective length of the velocity-saturation region. The dependence of l on device geometries and process parameters is investigated in this letter. From both experiment and two-dimensional (2-D) simulation, it is found that Emhas a form of (V_{DS} - V_{DSAT})/ 0.22Tmin{ox}max{1/3}Xmin{j}max{1/2}. Channel length affects the saturation voltage, thus influencing the maximum channel electric field. The scaling of oxide thickness and junction depth, however, often has even greater effects on channel field. This semiempirical model of Emagrees with Emdeduced from ISUBwithin about 5 percent; it can predict ISUB, which has been empirically correlated with hot-electron degradations.     

Short-channel MOSFET's in the punchthrough current mode

Results of two-dimensional device analysis are compared with experiment for 0.8-µm Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation (a critical factor which limits the maximum drain voltage of submicron MOS VLSI devices) with experiment and simulation has shown that the observed power-law dependence of IDSversusV_{DS} (V_{GS} = V_{SB} = 0)is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program (SUPREM) and device-simulation program (CADDET), is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.