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1.
本文研究了一种多模干涉型光波分复用器。采用导模传输分析法,给出了该光波分复用器的工作原理,在此基础上完成了该波分复用器的设计。然后根据所确定的器件结构参数,对该器件的插入损耗和隔离度进行分析。  相似文献   

2.
A 100-GHz optical pulse train is generated using an InP-based optical multiplexer. This device is based on a waveguide array with five paths of different lengths separated by a 10-ps propagation time. We used a multimode interference (MMI) splitter at the input and a taper-type combiner at the output. This device is well-suited for optical time-division multiplexing (OTDM) applications  相似文献   

3.
Bragg grating-assisted MMI-coupler for add-drop multiplexing   总被引:3,自引:0,他引:3  
This paper presents a novel device for add-drop multiplexing. The device is based on a Bragg grating-assisted multimode-interference (MMI)-coupler. The paper also presents computation results and design rules for this promising kind of add-drop multiplexer. The computation is based on the mode propagation theory, SiO2-Si is probably the most convenient technology for realizing this kind of device  相似文献   

4.
Optimal design of a multimode interference (MMI) coupler for broadening the spectral response of an arrayed-waveguide grating (AWG) demultiplexer is considered. By using a Gaussian beam approximation, an analytical expression for the spectral response of an AWG demultiplexer (with an MMI section) is obtained. A simple analytical formula is derived to relate the optimal MMI length to the separation between the peaks of the twofold images in the MMI region. This peak separation is related to the width of the MMI section. In the proposed design method, a required 1-dB passband width determines the peak separation, which then determines the optimal value for the length of the MMI section according to the analytical formula. The designed flat-top AWG demultiplexer is verified by the beam propagation method.  相似文献   

5.
In this paper, the multimode waveguide lengths and the output port locations of a SOI (silicon on insulator) material-based 1×4 MMI (multimode interference) optical splitter are optimized by means of FD-BPM (finite difference - beam propagation method). An improved 1×4 MMI optical splitter is designed. Compared with an usual optical splitter, a smaller loss 0. 12dB and a better output port power uniformity 0.11dB are achieved for the optical signal transmission.  相似文献   

6.
An ultracompact multimode interference (MMI) coupler based on Si nanowire waveguides is optimized to achieve polarization-insensitive performances. According to numerical simulations, an optimal width of the MMI section to achieve a polarization-insensitive performance is obtained for a fixed thickness of the core layer. A polarization-insensitive 1$,times,$2 MMI coupler with a size of about 3.8$mu$m$times$15.3$mu$m is designed as an example. Numerical simulations show that this optimized MMI coupler has a good fabrication tolerance (about$pm$45 and$pm$330nm for the MMI width and length, respectively) and the 0.5-dB bandwidth is more than 60 nm for both polarizations.  相似文献   

7.
In this paper, we develop mathematical theory for recursive construction of first-in first-out (FIFO) optical multiplexers by the combination of (bufferless) crossbar switches and fiber delay lines (SDLs). We show that by cascading multistage SDL units, 2-to-1 multiplexers with a large buffer can be emulated exactly for both the departure process and the loss process from the multiplexer. Such results are extended to the case of n-to-1 multiplexers by introducing a new class of multiplexers, called delayed-loss multiplexers. A delayed-loss multiplexer has the same departure process as an ordinary multiplexer. However, lost packets due to buffer overflow in a multiplexer might be delayed. A key result from our theory is the self-routing n-to-1 multiplexer, where the routing path of a packet through the multistage SDL units can be determined upon its arrival.  相似文献   

8.
Formulas based on scattering parameters are presented for the design of a multiplexer composed of n-1 channel equalizers connected either in parallel or in series at a common junction with a 1-Ω resistive generator and n-1 channel complex loads. It is shown as the singly-matched (S-M) multiplexer. A two-stage computer-aided design (CAD) approach is developed for the S-M multiplexer. A design example of a three-channel S-M multiplexer including the designs of three individual S-M channel equalizers is given to demonstrate the approach  相似文献   

9.
Ishida  O. 《Electronics letters》1994,30(25):2154-2155
A novel configuration is reported for a tunable channel-selection filter that employs an arrayed-waveguide grating (AWG) multiplexer and optical switches. The filter requires only 2(√N-1) 1×2 switch elements to select one of N frequency-division-multiplexed (FDM) channels. A filter for 100 GHz-spaced 16 FDM channels is demonstrated with an AWG 16×16 multiplexer and six 1×2 switches  相似文献   

10.
A 5 Cbit/s multiplexer using a step-recovery diode, microstrip transmission delay lines and fast p-i-n diode switches has been investigated. The signal/distortion ratio is 12 dB, where most of the distortion is due to an imperfect input signal. The overall multiplexer seems to be simple enough to be adopted in highcapacity optical-fibre communication systems.  相似文献   

11.
A quasi-optical frequency multiplexer based on a blazed diffraction grating is studied. Experimental data, supported by semi-quantitative theoretical considerations, show that the multiplexer is an efficient channel-dropping filter well suited to use in the millimeter wave region. A feature of the grating multiplexer which sets it apart from conventional designs is its ability to drop several channels using a single frequency-selective element, namely, a diffraction grating. This economy of hardware results in a simple, compact structure. The channels of the experimental multiplexer have typical bandwidths of ~540 MHz with loss of ~1 dB. The width of the impulse response at half amplitude is ~1.5 ns. Return loss within a channel is typically 15-20 dB. Comparisons with other millimeter wave multiplexer designs are discussed.  相似文献   

12.
A general multiplexer design procedure without dummy channels is described. The formulas are applied to the optimal design of practical contiguous or non-contiguous band multiplexers consisting of multicavity filters distributed along a waveguide manifold. All design parameters can be directly optimised. An example of a practical 12 channel, 12 GHz contiguous band multiplexer is presented.<>  相似文献   

13.
An ultracompact polarization-insensitive 1times2 multimode interference (MMI) splitter based on silicon-on-insulator is investigated theoretically. The impact of the insulator index on the size of the MMI and the polarization-dependent performance is analyzed. A polarization-insensitive 1times2 MMI splitter of 4 mum by 16.5 mum is shown as an example. Relaxed tolerances on MMI width (> plusmn100 nm) and length (> plusmn0.7 mum) are obtained for both polarizations while the polarization differential loss is kept in range of 0.1 dB and its excess loss is kept below 0.5 dB. In addition, a wide operation wavelength window of 150 nm is obtained for both polarizations as well.  相似文献   

14.
将时分复用的思路引入复用器中,提出TS流复用器的改进方案.该方案在消耗资源与控制处理方面都优干通用方法,对设计功能增强型的复用器具有一定参考价值.  相似文献   

15.
Vertically coupled microring resonators using polymer wafer bonding   总被引:3,自引:0,他引:3  
A new technique is presented to make vertically coupled semiconductor microring resonators that eases the fabrication process with devices more robust to ring-to-waveguide misalignments. Single-mode microring optical channel dropping filters are demonstrated for the first time in this configuration with Qs greater than 3000 and an on-resonance channel extinction greater than 12 dB. A 1×4 multiplexer/demultiplexer crossbar array with second-order microrings was also made and exhibited channel-to-channel crosstalk lower than 10 dB  相似文献   

16.
The 4:1-multiplexer reported here is based on a 21 GHz fT 0.4 μm silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is provided. A phase control circuit permits the choice of the optimum clock phase for the first and the second multiplexer stages; an internal delay line is not necessary. The 4:1-multiplexer consumes about 1.8 W with a single supply voltage of -4.5 V  相似文献   

17.
A novel 1×4 coupler multiplexer permutation switch (CMPS) is proposed for applications in wavelength-division-multiplexing (WDM) optical networks. The structure of the CMPS integrates the multiplexing and switching functions into a single compact device. It consists of a single-mode/multimode-waveguide grating-assisted, backward-coupler multiplexer followed by a 1×4 digital optical switch (DOS). The specific design uses an InP-based 1×4 CMPS with InGaAsP-InP multiple-quantum-well (MQW) DOS. The calculated values of crosstalk for the coupler multiplexer and the DOS are <-25 dB and -23 dB, respectively, giving an overall crosstalk <-21 dB for channel bandwidths of 10-13 GHz. The device channels are unequally spaced, which reduces unwanted four-wave mixing (FWM), but are fitted to the ITU standard wavelength grid  相似文献   

18.
A very high-speed 2:1 multiplexer IC operating up to 11.4 Gbit/s has been implemented. The circuit was fabricated using a 12 GHz non-polysilicon-emitter self-aligning bipolar process with 2 mu m lithography. Despite realisation in a relatively simple technology, this is the highest operating speed yet achieved with any technology.<>  相似文献   

19.
A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.  相似文献   

20.
提出了基于Stratix II系列FPGA的复用器硬件平台方案,对该平台的各个电路模块分别进行设计和测试,最终形成一个完整的复用器,单片FPGA实现片上系统,成本低,并利用FPGA的纵向移植特性,拓展复用器的复用路数,灵活方便。  相似文献   

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