基于有源匹配转换器的全集成双频带射频CMOS功率放大器的设计

设计了基于有源转换器的双频带射频CMOS功率放大器,该放大器可以应用于移动WiMAX系统. 设计采用了0.13μm CMOS 工艺并且所有的匹配完全集成在芯片内. 转换器可以通过有源匹配而在双频带工作,在2.5和3.5GHz,转换器的效率为78.2%和70.4%,功率放大器的增益分别为26.5和24.8dB,功率增加效率为20%和28%,在平均功率25dBm处,三阶交调系数均低于-30dBc.     

基于RF MEMS开关的新型双频带功率放大器

RF MEMS开关具有低损耗、低功耗、尺寸小和易于集成等优点而被广泛应用于各种可重构射频电路及系统中。通过分析比较电容并联式和串联式RF MEMS开关两种电路结构的射频性能,设计了一种基于RF MEMS开关的新型功率放大器,使用RF MEMS开关控制匹配网络来实现双工作频带的转换。结果表明,设计的功率放大器在2.35GHz和1.25GHz两个工作频带下,功率附加效率(PAE)和输出功率(Pout)可分别达到72%、67%及40.8、42.7dBm。该功率放大器具有较高的功率附加效率和输出功率,适用于多频带的射频系统,对RF MEMS器件在可重构系统中的应用具有一定参考价值。     

一种大功率高效率的Ku波段SiGe硅功率放大器设计

采用SiGe BiCMOS工艺设计了一款大功率高效率硅基功率放大器芯片,用于驱动现有大功率GaN功率放大器芯片,满足相控阵雷达的低成本需求。该硅基功率放大器通过和低噪声放大器、驱动放大器、数控移相器、数控衰减器、单刀双掷开关、电源管理以及数字逻辑单元等硅基电路进一步集成,实现了一片式高集成度硅基幅相多功能芯片,从而降低了前端收发组件的尺寸和成本。在硅基功率放大器设计中,结合Stack结构、变压器耦合结构和有源偏置结构,开展电路设计及优化,提高了放大器的输出功率和效率。测试结果表明:研制的硅基功率放大器在Ku波段f_1~f_2(3GHz带宽)频带内,实现了小信号增益31dB;在-3dBm输入功率条件下,实现发射功率21.5dBm、功率附加效率(PAE)25%等技术指标。集成功率放大器的幅相多功能芯片在f_1~f_2(3GHz带宽)频带内,实现了发射通道增益24dB;在5dBm输入功率条件下发射功率21.5dBm、功率附加效率(PAE)23%等技术指标。     

一种宽带高效率J类功率放大器的设计

针对未来无线通信系统中的宽带和效率问题,设计了一种宽带高效率的J类功率放大器。为了减少谐波阻抗对效率的影响,该J类功率放大器在输出匹配网络中采用了谐波控制单元,并通过对晶体管模型的简化,综合出一种较好的匹配网络。另外,在输入匹配网络中,使用了具有宽带效应的混合集中和分布元件的π形匹配网络。设计中使用10 W GaN HEMT晶体管对理论进行验证,测试结果显示,在2.2 GHz～2.8 GHz之间的频带内,J类功率放大器的漏极效率大于61%,增益大于10.4 dB。该J类功率放大器在下一代无线通信系统中具有良好的应用前景。     

模拟器件

ALM-31x22:功率放大器Avago推出1W和2W系列高性能放大器产品,面向新一代移动网络和WiMAX基础设施应用。ALM-31122/31222/31322系列1W基站用功率放大器产品可以支持750MHz到3.9GHz频带,ALM-31x22功率放大器内置有源偏压电路,无需射频匹配器件,可以简化客户的产品设计并加快产品上市速     

基于低通滤波匹配网络的双频功率放大器设计

提出了一种基于低通滤波匹配网络的高效率并发双频功率放大器设计方法。将连续F 类与连续逆F 类功放模式相结合,在保证效率的前提下拓展了阻抗设计空间,同时在谐波范围内引入多个传输零点,完成低通滤 波匹配网络的设计,对谐波进行抑制。为验证设计方法的合理性,设计制造了一款工作于1. 6 GHz 与2. 4 GHz 且带 宽超过200 MHz 的并发高效率功率放大器,在两频带内具有超过66%的功率附加效率以及超过40 dBm 的输出功 率,其相邻信道泄漏比也优于-25 dBc。     

基于负载牵引的S波段40W LDMOS功率放大器设计

摘要：针对LDMOS功率放大器在S波段的设计难点,文中介绍了基于负载牵引测试技术的LDMOS功率放大器设计方法。阐述了负载牵引的测试系统和测试原理,并对LDMOS预匹配管进行了负载牵引测试,利用测试结果设计了一个工作频率为2.7～3.1GHz的LDMOS功放。功放的测试结果显示,工作频带内输出功率大于40W,增益超过11dB,效率超过了40%。从而为LDMOS功率放大器在S波段的设计提供了良好的借鉴作用。     

8.5GHz～10GHz GaAs准单片功率放大器

文章介绍了一种准单片形式的功率放大器,采用南京电子器件研究所研制的12mm栅宽的GaAs pHEMT功率管芯,设计了准单片电路形式的匹配电路,设计所得的功率放大器在8.5GHz~10GHz频带范围内,输出功率典型值为5W,功率增益大于6dB,相对带宽大于16%,典型功率附加效率为25%,输入电压驻波比小于2.5。     

GaN HEMT工艺的X波段发射前端多功能MMIC

采用0.25 μm GaN HEMT 工艺,研制了一款X 波段发射前端多功能MMIC,片上集成了一个单刀双掷(SPDT)开关和一个功率放大器电路。其中SPDT 开关采用对称的两路双器件并联结构,功率放大器采用三级放大拓扑结构设计,电路采用电抗匹配方式兼顾输出功率和效率。测试结果表明,在8～12 GHz 频带内,芯片发射通道饱和输出功率为38.6～40.2 dBm,功率附加效率为29%～34.5%,其中开关插入损耗约为0.8 dB,隔离度优于-45dB。该芯片面积为4 mm×2.1 mm。     

12～15GHz 5W GaAs宽带内匹配功率管及其应用

报道了一种新型的砷化镓宽带高效内匹配功率放大器,它采用集总参数与分布参数相混合的匹配电路形式,取用南京电子器件研究所研制的12 mm功率PHEMT管芯,研制的内匹配功率放大器在12～15 GHz频带内,输出功率大于5 W,功率增益大于6 dB,相对带宽为25%,典型功率附加效率为25%。     

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.     

A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

A millimeter-wave power amplifier fabricated in 90 nm bulk CMOS technology consists of 3 identical cascode stages and on-chip matching networks (inter-stage, input, and output) implemented with wide-gap coplanar waveguides and M6-M5 (MIM) capacitors. The amplifier realizes a linear power gain of 19.7 dB at 52.4 GHz and 10.3 dB at 60 GHz. Maximum saturated output power and output-referred compression point are and 3.1 dBm, respectively. Peak PAE is 4.2%. The 1.180.96 die consumes 75 mA when operating from a 2 V supply.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

A 1.8-GHz CMOS Power Amplifier Using a Dual-Primary Transformer With Improved Efficiency in the Low Power Region

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.     

A 6-9 GHz ultra-wideband CMOS PA for China's ultra-wideband standard

A 6-9 GHz ultra-wideband CMOS power amplifier(PA) for the high frequency band of China's UWB standard is proposed.Compared with the conventional band-pass filter wideband input matching methodology,the number of inductors is saved by the resistive feedback complementary amplifying topology presented.The output impendence matching network utilized is very simple but efficient at the cost of only one inductor.The measured S_(22) far exceeds that of similar work.The PA is designed and fabricated with TSMC 0...     

Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm² power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P_1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.     

基于GaN HEMT 多倍频程高效率功率放大器设计

使用GaN HEMT 功率器件,设计了一款多倍频程高效率功率放大器。利用负载牵引技术分析输入功率、偏置电压、工作频率对功率器件输出阻抗的影响,从而寻找出满足宽带性能的最优阻抗区域;输入、输出匹配网络采用了切比雪夫多节阻抗变换器的综合设计方法,很好地拓展了匹配网络的带宽性能,从而实现了0. 8 ~4. 0 GHz(相对带宽133%)多倍频程高效率功率放大器电路。连续波大信号测试结果表明:在0. 8 ~ 4. 0 GHz 的频率范围内输出功率为39. 5 ~42. 9 dBm,漏极效率为54. 20% ~73. 73%,增益为9. 4 ~12. 0 dB。在中心频率2. 4 GHz 未利用线性化技术的情况下使用5 MHz WCDMA 调制信号测试得到邻近信道泄漏比(ACLR)为-27. 2 dBc。设计的工作频率能够覆盖目前主要的无线通信系统GSM900M、WCDMA、DCS1800 LTE、PCS1900 LTE、3. 5GHz WiMAX 以及下一代移动通信系统(5G)等。     

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.