A 125 μW , Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18mum one-poly six-metal CMOS technology with an area of 15.21 mm². For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 muW and 108 muW, respectively, at 1V supply voltage     

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-μm CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm×10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 μA, which is only 17% of that for the conventional CMOS design     

H.264中DCT/IDCT/Hadamard变换多时钟方式的FPGA实现

DCT/IDCT/Hadamard变换被广泛应用于多种视频编码标准中,而H.264/MPEG-4AVC作为新一代的视频压缩标准,它具有在相同图像质量下比其他视频压缩标准拥有更高的压缩率的特性[1],因此对于H.264/MPEG-4AVC中的DCT/IDCT/Hadamard变换的研究就有着十分重要的意义。对于H.264/MPEG-4AVC中变换算法进行分析,并且提出一种可用的高效的硬件实现电路结构,此电路结构能够并行计算4输入像素数据。     

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 × 6.5 mm² die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.     

用于H.264编解码的面向HDTV应用的动态可重构多变换VLSI结构

提出了一种新的支持MPEG-4 AVC/H.264标准4×4整数变换的动态可重构结构.首先,针对4×4正反变换分别推导了两个新的二维直接信号流图.进而设计了一个面向HDTV应用的动态可重构多变换结构.该结构无需转置寄存器且计算单元仅需16个加法器(减法器).采用0.18μm CMOS工艺实现了该电路结构.结果表明,最高...     

H.264/AVC在3G移动通信中的应用

H.264/AVC是目前最新,也是性能最优异的国际视频压缩编码标准。在相同的视频质量下,H.264/AVC可以比MPEG-4(SP)节省大约一半的带宽,同时还具有更好的网络适应性和传输健壮性,在3G移动通信系统带宽资源紧张、通信环境恶劣的情况下,H.264/AVC应该是目前最合适的选择。从压缩效率、网络适应性和健壮性3个方面分析了H.264/AVC的新技术,并讨论了它们在3G移动通信中的应用。     

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-/spl mu/m pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur.     

基于H.264的精细可伸缩性视频编码及实现

在MPEG-4精细可伸缩性编码的基础上，提出了一种基于H．264的精细可伸缩性视频编码方案。仿真和实验结果表明，在相同码率下，基于H.264的精细可伸缩性视频编码比基于MPEG-4的精细可伸缩性视频编码具有更高的信噪比和视觉质量。同时提出了基于H．264精细可伸缩性视频编码的视频点播系统的实现方案。     

General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding

The latest international video-coding standard H.264/AVC significantly achieves better coding performance compared to prior video coding standards such as MPEG-2 and H.263, which have been widely used in today’s digital video applications. To provide the interoperability between different coding standards, this paper proposes an efficient architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC intra frame transcoding, using the original information such as discrete cosine transform (DCT) coefficients and coded mode type. Low-frequency components of DCT coefficients and a novel rate distortion cost function are used to select a set of candidate modes for rate distortion optimization (RDO) decision. For H.263 and H.264/AVC, a mode refinement scheme is utilized to eliminate unlikely modes before RDO mode decision, based on coded mode information. The experimental results, conducted on JM12.2 with fast C8MB mode decision, reveal that average 58%, 59% and 60% of computation (re-encoding) time can be saved for MPEG-2, H.263, H.264/AVC to H.264/AVC intra frame transcodings respectively, while preserving good coding performance when compared with complex cascaded pixel domain transcoding (CCPDT); or average 88% (a speed up factor of 8) when compared with CCPDT without considering fast C8MB. The proposed algorithm for H.264/AVC homogeneous transcoding is also compared to the simple cascaded pixel domain transcoding (with original mode reuse). The results of this comparison indicate that the proposed algorithm significantly outperforms the mode reuse algorithm in coding performance, with only slightly higher computation.     

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low powermotion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAM's, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45×12.45 mm² chip with 0.35-μm CMOS and triple-metal layer technology are integrated 3.1 M transistors     

Fast Interframe mode decision algorithm based on mode mapping and MB activity for MPEG-2 to H.264/AVC transcoding

Recently the latest video coding standard H.264/AVC is widely used for the mobile and low bitrate video codec in the various multimedia terminals. On the other hand, the MPEG-2 MP@HL codec has become the center of digital video contents since it is the standard codec for the Digital TV (DTV). To provide the bridge between the contents in MPEG-2 and mobile terminals, the transcoding of MPEG-2 contents into H.264/AVC format is an inevitable technology in the digital video market. The main bottleneck in the process lies in the computational complexity. In H.264/AVC, the variable block size (VBS) mode decision (MD) is used in the Interframe for the improved performance in the motion compensated prediction. For the macroblock (MB) which cannot be accurately predicted with one motion vector (MV), it is partitioned into smaller blocks and predicted with different MVs. In addition, SKIP and Intra modes are also permitted in the Interframe MD of H.264/AVC to further ameliorate the encoding performance. With the VBS MD technology, the Inter prediction accuracy can be improved significantly. However, the incidental side-effect is the high computational complexity. In this paper, we propose a fast Interframe MD algorithm for MPEG-2 to H.264/AVC transcoding. The relationships between SKIP and Intra modes are detected at first to map these two kinds of modes directly from MPEG-2 to H.264/AVC. And then the MB activity will be scaled by the residual DCT energy obtained from the MPEG-2 decoding process to estimate the block sizes of the MB mode for H.264/AVC Interframe MD. In our proposed method, the original redundant candidate modes can be eliminated effectively, resulting in the reduction of the computational complexity. It can reduce about 85% Rate-to-Distortion Cost (RDCost) computing and 45% entire processing time compared with the well-known cascaded transcoder while maintaining the video quality.     

Video coding with H.264/AVC: tools, performance, and complexity

H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.     

基于H.264的FGS视频编码及其在视频会议系统中的应用

主要介绍视频会议系统的基本概念及其对视频编解码技术提出的要求,在MPEG-4精细可伸缩性编码(FGS)的基础上,提出了一种基于H.264的精细可伸缩性视频编码方案,仿真和实验结果表明,基于H.264的FGS具有更高的信噪比和视觉质量,能较好地满足基于IP的H.323视频会议系统不同终端的视频质量要求。     

3种主流HDTV压缩编码方法的比较

基于MPEG-4、H.264 High Profile及H.264 Main Profile等3种视频压缩编码方法,对HDTV(高清晰度电视)视频压缩标准中的算法进行了详细的分析和测试,分别从编码对象的率失真曲线、编码速度和High Profile在不同量化步长下的主观图像质量对3种压缩编码方法进行比较分析.测试结果表明:H.264 High Profile编码复杂度比MPEG-4提高了6倍～9倍,比H.264 Main Profile提高了20%～50%;从最佳编码性能角度考虑,H.264 High Profile是最适合于标清和高清晰度序列的编码方案.     

Video transcoding from H.264/AVC to MPEG-2 with reduced computational complexity

This paper addresses video transcoding from H.264/AVC into MPEG-2 with reduced complexity and high rate-distortion efficiency. While the overall concept is based on a cascaded decoder–encoder, the novel adaptation methods developed in this work have the advantage of providing very good performance in H.264/AVC to MPEG-2 transcoding. The proposed approach exploits the similarities between the coding tools used in both standards, with the objective of obtaining a computationally efficient transcoder without penalising the signal quality. Fast and efficient methods are devised for conversion of macroblock coding modes and translation of motion information in order to compute the MPEG-2 coding format with a reduced number of operations, by reusing the corresponding data embedded in the incoming H.264/AVC coded stream. In comparison with a cascaded decoder–encoder, the fast transcoder achieves computational complexity savings up to 60% with slightly better peak signal-to-noise ratio (PSNR) at the same bitrate.     

AVCHD高清摄像机及其视频格式

MPEG-4 AVC/H.264是目前最新的国际视频压缩标准,已被确定为下一代影视光盘(Blue-rayDisc)和HD DVD(高清DVD)的视频编码标准之一。简要介绍AVCHD高清摄像机的主要性能指标,重点对MPEG-4 AVC/H.264的特点和应用进行了分析。     

A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

We have developed an H.264/MPEG-4 dual video codec IP for mobile applications such as digital still cameras (DSCs), digital video cameras (DVCs), and mobile phones. The codec is capable of encoding and decoding HD-sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD-sized pictures at 54 MHz. We have implemented our original architecture based on a macroblock-level pipeline method and encoding algorithms suitable for the architecture in the codec, which enable low power of 64 mW for HD encoding with high picture quality equivalent to that of the H.264 reference encoder “JM (Joint Model)”.      

A real-time digital VCR encode/decode and MPEG-2 decode LSIimplemented on a dual-issue RISC processor

A real-time system large-scale-integrated circuit (LSI) for digital video cassette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performance and can execute fixed-length data processing at the block level as well as processing at the macro-block level and above for the DVCR/MPEG-2. The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables. The dedicated hardware for video-block loading can process video-block data transfers with half-pel operations. The LSI size is 7.7×7.2 mm² in a 0.25-μm CMOS process     

流媒体应用中TS和MP4格式分析

新一代视频编码标准H．264／AVC具有编码效率高，容错性强等特点，在流媒体传输应用方面有广阔的应用前景。介绍了一种典型的流媒体传输基本框架，对基本传输过程进行了介绍，分析了其中可能存在的问题，特别是传输和存储格式方面并根据通用的MP4和MPEG-2TS格式围绕着复用、同步、打包问题进行了重点研究。