PLL soft functional failure analysis in advanced logic product using fault based analogue simulation and soft defect localization

Soft defect localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across the device under test (DUT). This technique has proven its usefulness for quickly locating defects that are temperature, frequency, and/or voltage dependant, for example, scan logic soft fault. However, due to high sensibility at analogue circuits SDL meets great challenges. This work gives a new flow to analyze soft functional failure in advanced logic products using fault based analogue simulation and SDL. The paper will present one case study illustrating the application of analogue simulation based soft defect localization flow as an effective means to achieve fault isolation.     

基于SEM电压衬度的缺陷定位方法研究

光发射显微分析、光致电阻变化技术两种电失效定位方法在精确定位缺陷上存在局限性,为此提出了基于SEM电压衬度的联用方法用于精确定位集成电路缺陷。首先根据电特性测试进行光发射显微分析或者光致电阻变化分析,结合电路原理和版图,提出失效区域的假设,再进行电压衬度像分析,通过衬度翻转可精确和快速确定缺陷位置,最后通过FIB或者TEM对缺陷进行表征。案例研究显示,有源电压衬度可定位双极型电路铝金属化开路失效,无源电压衬度定位CMOS电路多晶硅栅刻蚀异常引起的漏电流失效,结合形貌和材料分析得出缺陷形成机理和根本原因。     

A dynamic synchronization method to realize soft defect localization applied on digital and mixed-mode analog ICs in failure analysis

Failure analysis on advanced logic and mixed-mode analog ICs more and more has to deal with so called ‘soft defects’. In this paper, a dynamic synchronization method is proposed to perform soft defect localization (SDL) technique by Optical Beam Induced Resistance Change (OBIRCH). It is a new and low-cost way to achieve SDL technique by OBIRCH equipment if there is no normal SDL equipment on hand. It extends the application of OBIRCH equipment to a more advanced failure analysis realm. The methodology and system configuration are presented. The experimental results show this dynamic synchronization method is accurate enough to locate a soft defect. Two real cases are studied on a digital IC and a mixed-mode analog IC respectively using this method.     

Application of time resolved emission techniques within the failure analysis flow

As the number of transistors and metal layers increases, traditional fault isolation techniques are less successful in exactly isolating the failing net or transistor to allow physical failure analysis. One tool to minimize the gap between global fault isolation – by means of emission microscopy or laser based techniques (TIVA, OBIRCH) – and physical root cause analysis is Time Resolved Emission (TRE). This paper presents two case studies illustrating the application of TRE within the failure analysis flow to generate a reasonable physical failure hypothesis.     

Layout analysis as supporting tool for failure localization: Basic principles and case studies

To be able to localize a defect on results obtained by failure analysis tools like emission microscopy or OBIRCH analysis it is necessary to understand the effect of a certain defect on an integrated circuit, as only some defects can directly be pinpointed by these analysis methods. In the majority of cases, only second order effects are visible, e.g., a floating gate will cause a transistor to emit light. In that case, the failure site differs from the point of emission.While the physical principles of common defects are well understood one has also to consider the layout of an integrated circuit. By matching the failure analysis results obtained by emission microscopy or OBIRCH analysis to the layout and schematics of a failing device it is possible estimate the root cause of the failure. Thus, the failure site can be narrowed down, to be finally able to proceed with the physical analysis for root cause determination.This paper will give an overview of physical failures that can occur and their effects on emission and OBIRCH analysis. These failure modes will then be correlated to the layout of a device in order to be able to estimate the root cause of a failure based on analysis techniques like emission microscopy and OBIRCH analysis. Finally, we will present case studies of successful failure localization based on layout analysis.     

Failure analysis defect location on a real case 55 nm memory using dynamic power supply emulation

Static and dynamic techniques for defect location are well established in the failure analysis flow of a failing integrated circuit. When a circuit shows an overconsumption on power supply, the useful static techniques are laser stimulation (OBIRCH, TIVA, LIVA, etc.) or photoemission. When the electrical signature is a soft fail, a functional fault or a timing issue the analyst will use dynamic techniques like dynamic laser mapping (SDL, xVM, LVI, etc.), dynamic photoemission or internal probing (Ebeam, TRE, LVP, etc.) by applying a looping test sequence which emulates the fail.In this paper we will present a real case analysis on a circuit showing a static signature (over consumption) and also a functional fault. Both static and dynamic location techniques have been used for the defect location, plus a non conventional approach by applying a clocked power supply sequence to the circuit. A comparison is done between the different signatures and we show that dynamic power supply emulation can bring some additional information on the defect location which is not detected with the conventional static/dynamic approach.     

基于失效物理的集成电路故障定位方法

超大规模集成电路后道工艺(BEOL)中的失效日益增多,例如多层金属化布线桥连、划伤,栅氧化层的静电放电(ESD)损伤、裂纹等失效模式,由于失效点本身尺寸小加上电路规模大,使得失效分析难度增加。为了能够对故障点进行快速、精确定位,提出了基于失效物理的集成电路故障定位方法。根据CMOS反相器电路的失效模式提出了4种主要故障模型:栅极电平连接至电源(地)、栅极连接的金属化高阻或者开路、氧化层漏电和pn结漏电。结合故障模型产生的光发射显微镜(PEM)和光致电阻变化(OBIRCH)现象的特征形貌和位置特点,进行合理的失效物理假设。结果表明,基于该方法可对通孔缺陷、多层金属化布线损伤以及栅氧化层静电放电损伤失效进行有效的定位,快速缩小失效范围,提高失效分析的成功率。     

Effect of physical defect on shmoos in CMOS DSM technologies

Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.     

Local thermal probing to detect open and shorted IC interconnections

A new failure analysis technique has been developed for backside and frontside localization of open and shorted interconnections on ICs. This scanning optical microscopy technique takes advantage of the interactions between IC defects and localized heating using a focused infrared laser (λ=1340 nm). Images are produced by monitoring the voltage changes across a constant current supply used to power the IC as the laser beam is scanned across the sample. The method utilizes the Seebeck Effect to localize open interconnections and Thermally-Induced Voltage Alteration to detect shorts. The interaction physics describing the signal generation process and several examples demonstrating the localization of opens and shorts are described. Operational guidelines and limitations are also discussed.     

电源管理IC失效模式验证及定位方法

电源管理集成电路(IC)的自动测试机(ATE)测试故障主要包括连续性失效、直流参数测试失效、交流参数测试失效和功能测试失效.ATE测试适用于大规模量产的不良产品的筛选,但是将ATE测试结果直接应用于失效分析依然存在覆盖局限性问题.针对不同功能测试结果,采用了不同的失效模式验证和分析方法.综合运用I-V曲线测试仪、示波器、函数发生器等仪器进行失效模式验证;使用微光显微镜、光诱导电阻变化仪器进行缺陷的失效定位;并借助电路原理图、版图进行故障假设;分析由过电应力、静电放电损伤、封装缺陷等导致的物理损伤;最终揭示了电源管理IC功能失效的主要原因.     

Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives

In this paper, we propose a novel test technique for fault detection and automated fault diagnosis using pole/zero analysis of embedded integrated passives. For performing pole/zero analysis, an ensemble of circuits obtained by perturbing the circuit under test parameters using their known statistical distributions is generated. From knowledge of the passive circuit specifications, the poles and zeros of every such circuit are extracted and pass and fail regions for the critical poles and zeros are computed in the real-imaginary plane. The proposed test technique uses a region-matching algorithm to detect faults and perform automated diagnosis of catastrophic and parametric faults using frequency domain 2-port measurements. A practical example is presented in order to verify the proposed pole/zero analysis using the fabricated embedded RC device.     

一种多电源域专用数字电路的静电失效分析及提升研究

在静电放电(ESD)能力考核时,一种多电源域专用数字电路在人体模型(HBM)1 700 V时失效。通过HBM测试、激光束电阻异常侦测(OBIRCH)失效分析方法,定位出静电试验后失效位置。根据失效分析结果并结合理论分析,失效是静电二极管的反向静电能力弱所致。利用晶体管替换静电二极管,并对OUT2端口的内部进行静电版图优化设计。改版后,该电路的ESD防护能力达2 500 V以上。该项研究结果对于多电源域专用数字电路的ESD失效分析及能力提升具有参考价值。     

Localization of sensitive areas of power AC switch under thermal laser stimulation

Thermal laser stimulation (TLS) is a widely used tool in a failure analysis laboratory to detect defects in integrated circuits. TLS can also be used for good device characterization. In this paper, we apply TLS – and especially optical beam induced resistance change (OBIRCH) method – to localization of electrically high stressed areas. We test this process with a new product from power AC switch family without failure. We localize several sensitive areas involved during and after switching, which are similar to the ones obtained by electrical simulations.     

Analysis of Iddq failures by spectral photon emission microscopy

In this work, a fast identification of I_ddq failures using spectroscopic photon emission microscopy (SPEMMI) is proposed. The spectra obtained from failure sites on the I_ddq failed chips were compared with the ones of known defective components. Four distinguishable spectra categories were identified. They were attributed to gate oxide breakdown, metal shorts, blackbody radiation, and ESD caused junction spiking. The focused ion beam (FIB) technique was used to look at the damage sites for confirmation of the SPEMMI results.     

Single-Link Failure Detection in All-Optical Networks Using Monitoring Cycles and Paths

In this paper, we consider the problem of fault localization in all-optical networks. We introduce the concept of monitoring cycles (MCs) and monitoring paths (MPs) for unique identification of single-link failures. MCs and MPs are required to pass through one or more monitoring locations. They are constructed such that any single-link failure results in the failure of a unique combination of MCs and MPs that pass through the monitoring location(s). For a network with only one monitoring location, we prove that three-edge connectivity is a necessary and sufficient condition for constructing MCs that uniquely identify any single-link failure in the network. For this case, we formulate the problem of constructing MCs as an integer linear program (ILP). We also develop heuristic approaches for constructing MCs in the presence of one or more monitoring locations. For an arbitrary network (not necessarily three-edge connected), we describe a fault localization technique that uses both MPs and MCs and that employs multiple monitoring locations. We also provide a linear-time algorithm to compute the minimum number of required monitoring locations. Through extensive simulations, we demonstrate the effectiveness of the proposed monitoring technique.      

Static fault localization of subtle metallization defects using near infrared photon emission microscopy

In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are described. In the logic circuitry, through the study of the defect-induced hot carrier emissions from the combinational logic gates, distinctive differences in emission characteristic between open and short defects are identified. Using this defect induced emission characterization approach, together with layout trace and analysis, the type of defect can be predicted. The defect physical location, which yielded no detectable hotspot signal, can also be narrowed down along the long failure net. This allows for the selection of the most appropriate physical failure analysis approach for defect viewing and thus achieving significant reduction in failure analysis cycle time. In the memory array, the weak emission from partially turned-on pass gate transistor is leveraged to localize marginal opens and shorts on the wordline node of the pass-gate transistor. These approaches are applied with great success in the foundry environment to localize yield limiting defects that resulted in SCAN and memory build-in self-test failure, without memory bitmap, diagnostic support or measurable I_DD leakage, on advanced technology nodes devices. A discussion on the factors that influence the success rate of this approach is also provided.     

Scan chain failure analysis using laser voltage imaging

Design-for-test methodologies have enabled considerable reduction in test time and improvement in defect isolation. Defects which impede correct operation of scan chains are a significant fraction of yield loss. Isolating these defects is an important but underserved activity.Image-based technologies examining an extended area of die are popular diagnostics techniques because they provide intuitive and useful results. Emission based microscopy and laser fault isolation techniques, both static and dynamic, are readily available. However, neither technique provides insight to specific timing characteristics of the IC. Photoemission microscopy suffers from decreasing signal strength at lower voltages, and laser techniques can be difficult to perform with production test setups, requiring involved test pattern and setup adaptation.In this paper, we describe two scan chain defect localization case studies using Laser Voltage Imaging [1] on 40 nm bulk CMOS technology operating at 0.9 V. Results are also compared to other diagnostics techniques, including software-based shift analysis and photoemission microscopy.     

Scanning spreading resistance microscopy for failure analysis of nLDMOS devices with decreased breakdown voltage

Scanning Spreading Resistance Microscopy (SSRM) is successfully applied to investigate failing nLDMOS test devices that exhibit a lowered break down voltage (BVDSS) in electrical test. Cross-sectional, two-dimensional maps of the local sample resistivity from fail and reference (pass) devices reveal significant differences of the dopant concentration in individual, specific regions. This important information enables unambiguous identification of the root cause of the device failure to be dopant related. Furthermore, from a set of hypothesis, which explains the failed electrical test, SSRM results confirm exactly one and rule out the other. These are two important steps towards root cause identification. Since a relative comparison of fail and pass SSRM scans is sufficient for this failure analysis, an extensive data calibration for the absolute dopant concentration by means of additional SSRM measurements on test samples with known dopant concentration is not required. The ability of SSRM to prove or disprove miscellaneous fail hypothesis even without data calibration makes this method a very powerful tool for analysis of dopant related failure types.     

Fault diagnosis and test of DNA sensor arrays by using IFA approach

This paper presents a fault analysis applied to a novel optical, label-free sensors array for DNA detection. The inductive fault analysis approach to extract and model the possible defects has been used. A critical equivalent resistance for the possible faults has been defined and it allowed defining the threshold values of current to discriminate the occurrence of the failures mechanisms. Particularly critical is the shorts occurrence: in this failure mode the current changes can generate a wrong information that can be confused with the current reduction due to DNA detection. At the end a test strategy for structural test is proposed.     

Physical failure analysis in semiconductor industry—challenges of the copper interconnect process

Since the copper interconnect dimensions shrunk continuously, physical failure analysis becomes increasingly important for process optimization. Failure localization and defect analysis in interconnect structures as well as analysis of barrier/seed step coverage are challenges of the copper inlaid technology. Failure localization in via chain test structures using voltage contrast analysis with SEM/FIB tools and OBIRCH and subsequent destructive failure analysis using FIB/SEM and TEM are described. The inspections of voids in copper interconnects and of buried residuals in vias are typical tasks for process monitoring, which make the application of leading-edge analytical techniques necessary. Barrier/seed step coverage analysis at via chains challenges both TEM sample preparation and analysis. 3D object reconstruction by electron tomography is a promising future method for this task.