Prediction of Conditions for Chloride–Hydride Epitaxy of Ga1 – yInyAs1 – xPx Layers Isoperiodic with GaAs and GaAs1 – xPx

Semiconductors - For obtaining multicomponent III–V solid solutions, the vapor-phase methods such as the chloride–hydride epitaxy, the epitaxy from organometallic compounds, and the...     

A 1 V, 0.53 ns, 59 μW Current Comparator Using Standard 0.18 μm CMOS Technology

Wireless Personal Communications - This letter aim to propose a current comparator based on simple current mirror which use single amplifier to reduce input offset, the improving symmetry current...     

45 nm/32 nm CMOS – Challenge and perspective

Production of 45 nm node CMOS has already started. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the introduction of ArF immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also the promising item. Variability is the biggest concern for 32 nm node SRAM. To overcome these difficulties, collaboration between device and circuit engineer is important.     

High-frequency, 6.2 Å pN heterojunction diodes

Sb-based pN heterojunction diodes at 6.2 Å, consisting of narrow bandgap p-type In_0.27Ga_0.73Sb and wide bandgap n-type In_0.69Al_0.41As_0.41Sb_0.59, have been fabricated and measured. These diodes show excellent electrical characteristics with an ideality factor of 1.2 and high current density. S-parameter measurements and subsequent analysis show that these diodes have RC-cutoff frequencies over 1 THz, making these diodes excellent choices for high-frequency applications, such as sub-harmonic mixers for frequency conversion.     

Band offsets at interfaces of (1 0 0)InxGa1−xAs (0 ⩽ x ⩽ 0.53) with Al2O3 and HfO2

The electron energy band alignment at interfaces of In_xGa_1?xAs (0 ? x ? 0.53) with atomic-layer deposited insulators Al₂O₃ and HfO₂ is characterized using combined measurements of internal photoemission of electrons and photoconductivity. The measured energy of the In_xGa_1?xAs valence band top is found to be only marginally influenced by the semiconductor composition. This result suggests that the observed bandgap narrowing from 1.42 to 0.75 eV when the In content increases from 0 to 0.53 occurs mostly through downshift of the semiconductor conduction band bottom. Electron states originating from the interfacial oxidation of In_xGa_1?xAs lead to reduction of the electron barrier at the semiconductor/oxide interface.     

A 0.33 V 2.5 μW cross-point data-aware write structure,read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS

Conventional data-aware structure SRAMs consume unnecessary dynamic power during the read phase due to the read-half-select issue. In this paper, a 9T-based read-half-select disturb-free SRAM architecture with the cross-point data-aware write strategy is proposed. Based on the proposed write-half-select and read-half-select disturb-free strategy, our 9T bitcell structure improves the read and write SNM by 2.5X and 2.4X compared to traditional bitcells. Furthermore, the proposed strategy and 9T bitcell structure can reduce the read power dissipation on bitline of the SRAM array by 5.14X compared with traditional SRAMs. Based on the proposed architecture, a 16Kb SRAM is fabricated in a 130 nm CMOS which is fully functional from 1.2 V down to 0.33 V. The minimal energy per cycle is 11.8pJ at 0.35 V. The power consumption at 0.33 V is 2.5 µW with 175 kHz. The proposed SRAM has 1.5X and 4.2X less total power and leakage power than other works.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

Direct measurement of optical phase difference in a 3 × 3 fiber coupler

The precise phase difference in a 3 × 3 coupler is calculated by using Fourier transform based white-light interferometry. The phase relationships between any two of the three outputs are directly measured, and the result is in agreement with the ideal value. The phase difference of two re-constructed signals in a 3 × 3 coupler is also measured. In a passive homodyne system, this technique is helpful in removing the distortion of the demodulated signals, which is caused by imperfect properties of the 3 × 3 coupler.     

Erratum to: First-Principles Investigation of Electronic Properties of GaAsxSb1 – x Ternary Alloys

Semiconductors - erratum     

A low power voltage limiter for a full passive UHF RFID sensor on a 0.35 μm CMOS process

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 μm CMOS technology.     

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

With the rapid growth of computational intelligence techniques, automatic age estimation has achieved efficiency and accuracy that benefited IC aging-mitigation applications. This paper proposes an adaptive anti-aging system scheme that uses an intelligent algorithm to monitor the frequency degradation of digital circuits. An on-chip reliability sensor with voltage controlled oscillator (VCO) architecture achieved the circuit's aging rate, featuring real-time monitoring and tolerance against PVT variations. Cuckoo intelligence-based algorithm with global search strategy could obtain the accuracy data, reduce the number of iterations, and improve use self-adjust efficiency. The loop circuit can be quickly corrected by precise voltage compensation to alleviate performance degradation. The test chip was fabricated in the TSMC 65-nm CMOS technology with a core area of 0.97 mm². The measurement results show that the resolution is 0.004% at 1.2 V and 27 °C and a self-adjust time (SAT) reaches about 1.8 μs with an operating frequency of 500 MHz, recovering at 10% aging-related degradation. In comparison with other related literatures, the resolution of the proposed method is improved by more than 2.5 times.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Performance verification of tera-bit transmissions using 30 ch×40 Gb/s WDM signals over NZDSFs

We investigate the performance of Tbps transmissions using wavelength-division multiplexing (WDM) technologies based on the 40 Gbps line rate. To find the optimum conditions, the transmission performance is theoretically evaluated for various fiber types. To confirm modeling, the transmission performance is experimentally measured for TWF transmissions over 85 and 342 km. Bit error rates (BERs) and eye-diagrams have been calculated and measured to investigate the system performance. All the channels have characteristics of error free transmission. The calculated BERs and eye-diagrams have a good agreement with the experimental results.     

第十九讲 未来网络技术发展趋势

(上接第17期) Internet是未来网络的主体,IP技术是实现计算机互联网、传统的电话网和广电的有线电视网三网融合的关键技术.下一代网络是建立在IP技术基础上的新型公共电信网络,能够容纳各种形式的信息,在统一的管理平台下,实现音频、视频、数据信号的传输和管理,提供传统的电信业务和各种带宽的应用,是一个真正实现宽带窄带、有线无线、有源无源、传输接入一体化的综合业务网络.可以肯定地说:我们将会很快迎来一个真正综合的、宽带域、多功能、可以随时随地满足人们多角度、全方位需求的通信方式.     

An ultra-wideband 6–14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution

This paper describes the design and verification of an ultra-wideband 6–14 GHz frequency modulated continuous wave (FMCW) primary radar system with very high range resolution. The design and measurement results of the utilized signal generator and receiver are presented. The signal generator features a 86% relative continuous tuning range and average phase noise of −106 dBc/Hz at 1 MHz offset to the carrier. The radar system utilizes a hybrid structure where the voltage controlled oscillator was fabricated using 130 nm SiGe BiCMOS technology and the lower frequency components are off-the-shelf. Free field measurements of the radar showcase an unprecedented combination of 3 cm range resolution, low phase noise and low operating frequency of 6–14 GHz for inherently higher range.     

A genetic algorithm with chromosome-repairing for min − # and min − ε polygonal approximation of digital curves

A genetic algorithm for solving min ? ε polygonal approximation and min ? # polygonal approximation is proposed in this paper. It combines traditional split-and-merge techniques with a novel chromosome-repairing scheme to cope with constraints. Due to this combination of techniques we call our new method SMCR. In this new scheme an infeasible solution cannot only be easily transformed into a feasible one, but also be optimized. The experimental results show that the proposed SMCR has higher performance than the other GA-based methods and some non-GA-based methods.