A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance

Work function tuning of nickel silicide (NiSi) gates was utilized to fabricate a novel split-gate MOSFET with improved device performance. The MOSFET with a NiSi split gate has been achieved by implanting antimony into the polysilicon gate from the drain side with a tilt angle, followed by a full nickel-silicidation process. The laterally nonuniform antimony implantation causes the NiSi gate work function to vary from the source side to the drain side due to the dopant segregation effect. Improved current drive and output resistance are observed in the MOSFET with such a NiSi split gate. Metal gate advantages and NiSi process simplicity were also realized in the split-gate process, and gate oxide quality did not degrade due to the low temperature process. This split-gate design is expected to be applicable in the nanoscale regime by optimizing process conditions.     

Ni/Pd/Si固相反应及NiSi热稳定性增强研究

研究了Ni/Pd双层薄膜在硅衬底上的硅化物形成过程.结果表明,加入Pd层后,退火形成Ni1-xPdxSi固熔体,该固熔体比NiSi的热稳定性好,使得NiSi向NiSi2的转变温度升高.加入Pd的量越多,NiSi2的成核温度越高,并用经典成核理论解释了该现象.     

Structural and electrical characterization of platinum (~15 at%) doped nickel silicides on Si(100) and SiGe/Si(100) substrates

Ni(Pt~15 at%)Si/Si(100) and Ni(Pt~15 at%)SiGe/SiGe/Si(100) films corresponding to rapid thermal annealing (RTA1) temperatures of 220, 230 and 240 °C with constant RTA2 (at 420 °C) have been investigated for sub 20 nm devices. X-ray reflectometry (XRR), X-ray diffraction (XRD), four point probe, and atomic force microscopy (AFM) techniques were employed for the characterization of NiSi and NiSiGe films. XRR results indicated that NiSi and NiSiGe film thicknesses increased with RTA1 temperatures. NiSi films densities increased with layer thickness but NiSiGe films displayed an opposite trend. The diffractograms revealed that NiSi and NiSiGe layers contain identical phases and possessed fiber texture at 220 °C. Whereas, the peaks shift were observed for NiSi (211) and NiSi (021) at higher RTA1 temperatures which appear due to Pt diffusion (hexagonal structures of larger grain size were noted). NiSiGe crystallites self-alignment was observed because of strained SiGe/Si(100) substrate. At 240 °C, NiSiGe layer showed the smallest crystallites. This is believed to be due to Pt distributed along the silicide grain boundaries which obstructs silicide grain growth. NiSi and NiSiGe sheet resistance decreased significantly with increase in RTA1 temperatures and found to correlate with multiple grain orientation. AFM revealed a smooth-stable surface morphology for all films.     

Ni and Ti silicide oxidation for CMOS applications investigated by XRD,XPS and FPP

Although silicide oxidation was studied 20 years ago, the interest of obtaining a robust process for new application appears significant today. Indeed, for the new architectural development process are required dense and narrow spaces. This paper focuses to bury a silicide layer under a protective layer such as silica in order to keep constant the physical and electrical properties of silicide after oxidation. Earlier works show the possibility to oxidize preferably the silicon (Si) in metal contained silicide rather than a pure crystalline Si at high temperatures. Thus, we first tried to reproduce and study these conditions and once acquired, targeted to decrease the oxidation temperature in order to fit with industrial requirements. Titanium (Ti) and Nickel (Ni) are chosen for their metallurgical interest and their integration capability in devices. Thus, four different group/phases (TiSi, TiSi₂, Ni₂Si, NiSi) of silicide were targeted by adjusting the temperature. In situ X-ray diffraction (XRD), photoelectron spectroscopy and sheet resistance (four point probe) measurements were carried out simultaneously before and after oxidation of silicide to characterize the phase and chemical composition. After silicide formation last three phases (TiSi₂, Ni₂Si, NiSi) were confirmed by XRD and G1(Ti/Si) was unknown, where only for NiSi was observed the low sheet resistance (≈7.3 Ω/□) and resistivity (18 μΩ·cm). After (dry, wet and plasma) oxidation, the phases of TiSi₂ and Ni₂Si changed and only NiSi was observed the constant phase, even pure SiO₂ was noted on NiSi after wet oxidation.     

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co–Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co–Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni₂Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi₂ at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.     

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

We report a new method of forming nickel silicide (NiSi) on n-Si with low contact resistance, which achieves a Schottky barrier height of as low as 0.074 eV. Antimony (Sb) and nickel were introduced simultaneously and annealed to form NiSi on n-Si (100). Sb dopant atoms were found to segregate at the NiSi/Si interface. The devices with Sb segregation show complete nickel monosilicide formation on n-Si (100) and a close-to-unity rectification ratio. The rectification ratio R_c is defined to be the ratio of the forward current to the reverse current, where the forward and reverse currents are measured using forward and reverse bias voltages, respectively, having the same magnitude of 0.5 V. This process is also compatible and easily integrated in a CMOS fabrication process flow.     

Thermal stability of Ni silicide films on heavily doped n and p Si substrates

Electrical and structural properties of Ni silicide films formed at various temperatures ranged from 200 °C to 950 °C on both heavily doped n⁺ and p⁺ Si substrates were studied. It was found that surface morphology as well as the sheet resistance properties of the Ni silicide films formed on n⁺ and p⁺ Si substrates at the temperatures higher than 600 °C were very different. Agglomerations of Ni silicide films on n⁺ Si substrates begin to occur at around 600 °C while there is no agglomeration observed in Ni silicide films on p⁺ Si substrates up to a forming temperature of 700 °C. It was also found that the phase transition temperature from NiSi phase to NiSi₂ phase depend on substrate types; 900 °C for NiSi film on n⁺ Si substrate and 750 °C for NiSi film on p⁺ Si substrate, respectively. Our results show that the agglomeration is, especially, important factor in the process temperature dependency of the sheet resistance of Ni silicides formed on n⁺ Si substrates.     

Nickel silicide as a contact material for submicron CMOS devices

Nickel monosilicide (NiSi) is an attractive alternative to the currently used silicides for the coming generations of deep submicron complementary metaloxide-semiconductor (CMOS) devices. This silicide material has a resistivity, which is comparable to that of TiSi₂ or CoSi₂, but consumes less silicon for its formation. The silicide silicon interface is relatively planar and, unlike TiSi₂, its resistivity does not change with the linewidth for narrow lines. However, the thermal stability of NiSi is relatively poor at the currently used temperatures during process integration. Recent studies have shown that the stability of these films could be increased substantially through the small addition of alloy elements, which do not increase the resistivity of the NiSi film. Morever, it has been demonstrated that the addition of a small amount of alloy elements significantly reduces diode leakage, possibly due to the suppression of silicide spike formation as a result of alloy addition. This paper will present and discuss the details of these experimental results.     

Tuning of the Nickel Silicide Schottky Barrier Height on p-Type Silicon by Indium Implantation

In this letter, indium (In) implantation is introduced as a method to tune the Schottky barrier height of nickel silicide (NiSi) contacts formed on p-type silicon. Indium implantation is performed prior to NiSi formation and the implant conditions are chosen such that the implanted region is entirely consumed by the silicide. During silicide formation, some of the indium segregates at the NiSi–Si interface and can have a significant impact on the Schottky barrier height. It is shown that the barrier height decreases almost linearly with the In dose from 0.37 eV on p-type Si to 0.16 eV with an In dose of $hbox{1} times hbox{10}^{14} hbox{cm}^{-2}$ on p-type Si.      

NiSi contact metallization using electroless Ni deposition on Pd-activated self-assembled monolayer (SAM) on p-type Si(1 0 0)

In this paper we describe a method to form NiSi contacts using electroless plating of Nickel or Ni alloy on Pd activated self-assembled monolayer (SAM) on p-type Si(1 0 0). Such method allows uniform deposition of very thin, <30 nm, Ni or Ni alloy films. Clean, oxide free, Si substrate was covered with aminopropyltriethoxysilane (APTES) self-assembled monolayer. The surface was activated with Pd-citrate solution followed by electroless plating. The samples were annealed for 1 h in vacuum (∼10⁻⁶ Torr) forming the silicide layer. The annealing temperatures were 400 °C for NiP alloy and 500 °C for NiPW alloy. X-ray diffraction (XRD) measurement confirmed the presence of NiSi phase after annealing. The silicides material properties were characterized using secondary electron microscopy (SEM) analysis, X-ray diffraction (XRD) and X-ray photon spectroscopy (XPS) profiling. The results are reported and summarized.     

Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon–Carbon Source/Drain Stressors

We explore a novel silicide contact technology for effective Schottky barrier height Phi_Bn and contact resistance reduction, which is compatible with an advanced silicon-carbon (Si_1-xC_x) source/drain (S/D) stressor technology. The new silicide contact technology incorporates selenium (Se) that is coimplanted with S/D dopants into the silicon-carbon S/D prior to nickel silicidation, leading to the segregation of Se at the NiSi:C/n-Si_0.99 C_0.01 interface and the achievement of excellent ohmic contact characteristics. We demonstrate that the Se-coimplantation process contributes to a 23% drive current enhancement in a strained silicon-on-insulator n-MOSFET. The enhancement is attributed to the decrease of external series resistance which is primarily due to the reduction of silicide contact resistance.     

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi₂ were possible for thicker films depending on anneal temperature and time. Activation energy of 2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi₂ is higher than for morphological degradation.     

Arsenic redistribution induced by low-temperature Ni silicidation at 450°C on shallow junctions

Redistribution of arsenic (As) during silicidation of a 13-nm Ni film on an n⁺/p junction at 450°C is investigated. NiSi formation is observed by x-ray diffraction, micro-Raman scattering spectroscopy, and Rutherford backscattering spectroscopy (RBS). Both secondary ion mass spectroscopy and RBS data indicate the redistribution and accumulation of As into two layers after the low-temperature annealing. The deeper accumulation peak, located just near the silicide/silicon interface, is attributed to As segregation from silicide into Si substrate. The shallower accumulation peak is located in a vacancy-cluster layer several nanometers below the silicide film surface. The vacancy-cluster layer, characterized by cross-sectional transmission electron microscopy, separates the silicide film into two layers, and is attributed to the well-known Kirkendall effect.     

固相反应和离子注入制备硅化镍薄膜

采用固相反应和镍离子注入硅方法分别制备了硅化镍薄膜，利用卢瑟福背散射谱（RBS) , X射线衍射（XRD）和喇曼光谱对它们的成分和结构进行了表征. 结果表明固相反应方法中，硅化镍薄膜的相结构取决于不同的热退火条件，纯相的NiSi2薄膜需要在高温（1123K）下两步热退火才能获得. 而利用离子注入方法，则可以在较低温度（523K）下直接得到单相的NiSi2薄膜. 在30～400K范围内测量了它们的电阻率和霍尔迁移率随温度的变化关系，结果表明固相反应制备的NiSi和NiSi2薄膜都表现出典型的金属性电导行为，而离子注入制备的NiSi2薄膜则表现出完全不同的电学性质.     

Ni(W)Si/Si肖特基势垒二极管电学特性研究

文中首次提出在Ni中掺入夹层W的方法来提高NiSi的热稳定性。具有此结构的薄膜,经600℃～800℃快速热退火后,薄层电阻保持较低值,小于2Ω/□。经Raman光谱分析表明,薄膜中只存在NiSi相,而没有NiSi2生成。Ni(W)Si的薄层电阻由低阻转变为高阻的温度在800℃以上,比没有掺W的镍硅化物的转变温度的上限提高了100℃。Ni(W)Si/Si肖特基势垒二极管能够经受650℃～800℃不同温度的快速热退火,肖特基接触特性良好,肖特基势垒高度为0.65eV,理想因子接近于1。     

The influence of dopant species on thermal stability of NiSi film

We investigated the relationship between thermal stability of NiSi films and the implanted dopant species on Si substrates. The most stable NiSi layer appeared on Boron-implanted Si substrate, where the formation of pseudo-epitaxial transrotational structure was observed, just in case that the dose of boron is more than 5e15 atoms/cm². This unique crystallographic orientation of NiSi film on Boron-implanted substrate is a key role of thermal stability because thermal stress at grain boundary can be diminished by peculiar arrangement of transrotational domains, owing to the anisotropy in coefficient of thermal expansion (CTE) of NiSi.     

Fabrication of metal gated FinFETs through complete gate silicidation with Ni

Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors. NiSi-gate workfunction control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi/sub 2/. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance.     

Threshold voltage control in NiSi-gated MOSFETs through SIIS

Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.     

Electrical Properties of nMOSFETs Using the NiSi:Yb FUSI Electrode

In this letter, nMOSFETs using a NiSi:Yb fully silicide (FUSI) electrode are demonstrated for the first time. We report that the integration of NiSi:Yb FUSI into our reference n-FETs with the respective SiON / HfSiON gate dielectrics results in a V_t reduction from 0.55/0.52 down to 0.30/0.43 V, without degradation of the gate dielectric integrity, channel interface states, and long channel device mobility     

Electrical characteristics of thin Ni2Si,NiSi, and NiSi2 layers grown on silicon

We have determined the resistivity, carrier concentration, and Hall mobility as a function of thickness (700–3000 Å) of Ni₂Si, NiSi, and NiSi₂ layers formed by vacuum annealing at 270÷v300°C, ≈ 400°C, and ≈ 800°C, respectively, of nickel films vacuum-deposited on a silicon substrate (111 n-type and 100 p-type Si ρ ≈ 1KΩ). The layer thicknesses were measured by 2 MeV⁴He⁺ backscattering spectrometry. The silicide phase was confirmed by x-ray measurements. The electrical measurements were carried out using van der Pauw configuration. We found the electrical transport parameters to be independent of the film thickness within the experimental uncertainty. The Hall factors were assumed to be unity. The majority carriers are electrons in NiSi and holes in Ni₂Si and NiSi₂. The resistivity values are 24±2, 14±1, and 34±2 μΩcm, the electron concentrations are 9±3, 10 and 7±1, and ≈ 2 × 10²² cm^?3, and the Hall mobilities are 3±1, ≈ 4.5 and 6, and ≈ 9 cm²/Vs for Ni₂Si, NiSi (〈100〉 and 〈111〉), and NiSi₂, respectively. The systematic error in the measured values caused by currents in the high resistivity substrate is estimated to be less than 6% for the Hall coefficient. The results show that Ni₂Si, NiSi, and NiSi₂ layers formed by a thin film reaction are electrically metallic conductors, a result which concurs with those reported previously (1) for refractory metal silicides. The Hall mobility increases with the Si content in the silicide. The electron concentration is lowest for NiSi₂ leading to the highest resistivity for the epitaxial phase of NiSi₂.