圆片级测试MEMS器件的解决之道

MEMS产业发展十分迅速,但是人们常常忽视对其的早期测试。乍一看来,MEMS器件和传统IC器件的制造十分相似,但是,由于MEMS器件具有额外的机械部分（大多是可活动的）和封装,这些部分的成本通常占其总成本的大部分,因此MEMS器件的特性比传统IC器件要复杂得多,而且各不相同。     

新型MEMS微致冷器可行性研究

MEMS的高能量密度驱动和IC高度集成使MEMS器件严生较强的热效应,影响了MEMS器件的稳定性和寿命。传统的致冷器与待致冷器件是相对独立的器件,无法满足MEMS器件局部有效致冷和系统集成的要求。介绍了一种新型铁电薄／厚膜MEMS微致冷器的原理和设计,探讨其作为MEMS致冷器的可行性,该致冷器可以在较大工作温度范围内,对基于IC硅工艺的MEMS器件和普通IC芯片进行致冷。     

基于微谐振器的圆片级真空封装真空度测试技术

针对微电子机械系统(MEMS)圆片级封装腔体体积小、传统的真空封装测试方法适用性差的情况,研制了一种用于表征圆片级真空封装真空度的器件——MEMS微谐振器。利用此谐振器不仅可以表征圆片级真空封装真空度,也可用于圆片级真空封装漏率的测试。采用MEMS体硅工艺和共晶圆片键合技术实现了微谐振器的圆片级真空封装,利用微谐振器阻尼特性建立了谐振器品质因数与真空度的对应关系,通过设计的激励电路实现了微谐振器品质因数的在片测试,对不同键合腔体真空度下封装的MEMS微谐振器进行测试,测试结果显示该微谐振器在高真空度0.1～8 Pa范围内品质因数与真空度有很好的对应关系。     

圆片级封装技术——超CSP~(TM)

文章论述了超CSPTM圆片级封装技术工艺。在封装制造技术方面此CSP封装技术的优越性在于其使用了标准的IC工艺技术。这不仅便于圆片级芯片测试和老炼筛选,而且在圆片制造末端嵌入是理想的。同时,文章也论述了超CSP封装技术的电热性能特征。     

MEMS器件的封装材料与封装工艺

随着各种MEMS新产品的不断问世,先进的MEMS器件的封装技术正在研发之中.本研究综述了MEMS的封装材料,包括陶瓷、塑料、金属材料和金属基复合材料等.阐述了MEMS的主要封装工艺和技术,包括圆片级封装、单芯片封装、多芯片组件和3D堆叠式封装等.并展望了MEMS器件封装的应用和发展前景.     

圆片级组装、测试一体化的后道工艺

<正> 为了在半导体后道制造工艺中有效地应用摩尔比例缩小定律,必须要有一体化的圆片级封装工艺,并且,它可以以圆片的形式进行测试、老化和其它操作。到目前为止,已有多种圆片级封装技术的报导,但几乎都没有涉及到圆片级的测试和老化问题。一种新的技术可以使圆片级 CSP(芯片尺寸封装)、圆片级测试和最终组装一体化。其核心技术是直接在圆片上制作微弹簧接触器。这类接触器已被25个以上半导体厂家和测试工厂广泛用于高平行度探针卡上。圆片上的接触器,在老化和测试中被用作柔性弹性接触接口,在组装中被用作一级互连——焊接或插接芯片到衬底上。     

用于高级DRAM测试的单次触压、全晶圆探针

1Td300全晶圆探卡是一款用于高级DRAM存储器件单次触压、高容量测试的探卡，该产品使用专有的全晶圆架构和基于MEMS的ACCU-TORQ弯曲探针进行非常平滑的单次触压测试。该产品能够对300mm或200mm晶圆进行高并行测试（highly parallel testing）。每探针只需要2g压力就能够测试整个300ram晶圆，1Td300探卡提供了双重优势，不仅能够降低对被测晶圆和整个测试台的压力，同时允许更高的引脚数，以拓展半导体测试范围，     

满足各种挑战的WCSP封装持续增长

晶圆级芯片尺寸封装（WCSP）消除了类似传统的芯片键合、引线键合和倒装芯片贴装过程的封装工序。这种办法可以为半导体产品用户实现更快的上市时间。WCSP封装应用空间正在扩大到新的领域,并根据管脚数量和器件类型进行细分。WCSP封装正在集成无源、分立元件、射频和存储器器件方面得到应用,并扩展到逻辑集成电路和MEMS器件。但伴随着这种应用的增长出现了很多问题,其中包括随着芯片尺寸和管脚数量的增长对电路板可靠性的影响。概述当今的挑战,以及这些集成和硅通孔技术的未来趋势。     

晶圆上测试射频系统级芯片的挑战(英文)

随着无线通讯产业推动芯片集成度的不断提高,系统级封装(SIP)和多芯片组件(MCM)被更多采用,射频系统级芯片(RF-SOC)器件的良品测试已成为一大挑战。这些器件与传统的单晶片集成电路相比,具有更高的封装成本,并且由于采用多个晶片,成品率较低。其结果是进行晶圆上综合测试的成本远超过最终封装后测试器件的成本。此外,一些IC制造商销售裸晶片以用于另一些制造商的SIP和MCM中,这就要求发货的产品必须是良品。以蓝牙射频调制解调芯片为例,讨论了RF-SOC器件良品晶片(KGD)的测试难点和注意事项。对此样品,除了在晶圆上进行射频功能测试的难点,还有同时发射和测量数字、射频信号的综合问题。此外对被测器件(DUT)用印制线路板布线的难点,包括晶圆探针卡的设置及装配进行探讨。还介绍了选择探针测试台、射频晶圆探针卡和自动测试设备(ATE)时需考虑的因素。并以晶圆上测试的系统校正,包括难点和测试方法,作为结尾。这颗蓝牙射频调制解调芯片的实际测试数据也会被引用,以佐证和加深文章中的讨论。     

硅MEMS器件加工技术及展望

介绍了几种典型的硅基MEMS加工技术以及应用,并简单展望了MEMS加工技术发展趋势。硅基MEMS加工技术主要包括体硅MEMS加工技术和表面MEMS加工技术。体硅MEMS加工技术的主要特点是对硅衬底材料的深刻蚀,可得到较大纵向尺寸可动微结构,体硅工艺包括湿法SOG(玻璃上硅)工艺、干法SOG工艺、正面体硅工艺、SOI(绝缘体上硅)工艺。表面MEMS加工技术主要通过在硅片上生长氧化硅、氮化硅、多晶硅等多层薄膜来完成MEMS器件的制作,利用表面工艺得到的可动微结构的纵向尺寸较小,但与IC工艺的兼容性更好,易与电路实现单片集成。阐述了这些MEMS加工技术的工艺原理、优缺点、加工精度、应用等。提出了MEMS加工技术的发展趋势,包括MEMS器件圆片级封装(WLP)技术、MEMS工艺标准化、MEMS与CMOS单片平面集成、MEMS器件与其他芯片的3D封装集成技术等。     

Anti-buckling S-shaped vertical microprobes with branch springs

We propose the S-shaped vertical probes with branch springs for the wafer-level testing of IC chips. The conventional S-shaped vertical probe requires a guide structure to prevent buckling due to the large overdrive actuation involved. However, the guide structure not only increases the cost of fabrication, but it also requires a troublesome assembly procedure. In this paper, we present the S-shaped vertical probe with branch springs on the left and right sides of the main spring to prevent buckling. This probe was designed using finite-element methods and fabricated using Ni-Co electroplating. The performances of the probe for the wafer-level testing of IC chips were measured with the probe test equipments. Compared to the identical conventional S-shaped probe, the proposed probe has the overdrive (60 μm) that is 1.2 times larger and the contact force (25 mN) that is 2.5 times larger. This new S-shaped vertical probe satisfies the design requirements for a vertical probe without the guide structure and has the potential for use as a cost-effective guide-free probe card for the wafer-level testing of IC chips.     

Silicon cantilever arrays with by-pass metal through-silicon-via (TSV) tips for micromachined IC testing probe cards

In this paper, an integrated probe card is proposed and developed for wafer-level IC testing. Based on micromachining technology, totally about 26,000 cantilever-tip probes can be formed simultaneously in one 4-in. silicon wafer, with the minimum pitch of 35 μm for adjacent probing tips. The probe card is designed with a novel composite structure that combines both single-crystalline silicon and electroplated metals. In the composite structure, a novel bypass through-silicon-via with a low aspect ratio can be high-yield fabricated for transferring the testing signals from the probing sided (at the wafer bottom side) to the I/O interface (at the front side). The probe card makes full use of the advantages of the single-crystal silicon and the electroplated nickel and copper. Bulk micromachined silicon cantilevers behave uniform probing height and a good elastic deformation property, while the electroplated nickel probing tips promise high hardness and satisfactory electric contact performance with the dies-under-test (DUT). Measurements show that the fabricated cantilever is able to withstand a contact force of 80mN by a tip displacement of 20 μm. The measured contact resistances on metal pads (Al, Cu, and Au) are all below 1 Ω, whereas the maximum current leakage is 64 pA for 3.3 V voltage across two adjacent tips. After a probing reliability test of 100,000 cycles, the cantilever-tip shows no sign of any performance degradation.     

Application of a Genetic Algorithm to the Design Optimization of a Multilayer Probe Card for Wafer-Level Testing

The number of input and output pads on high-performance IC devices has increased in recent years, and hence wafer-level testing is conventionally performed using a probe card with a multilayer needle layout. This paper employs ANSYS commercial software and a Genetic Algorithm (GA) to optimize the design parameters of a multilayer needle probe card such that the scrub marks produced by the different needle layers are of approximately equal length. A dummy probe card containing both a conventional multilayer needle layout and the optimized needle layout is then fabricated and used in a series of single-contact probing tests. The results reveal that the scrub marks produced by the optimized needle layout are both shorter and of a more uniform length that those produced by the conventional needle design. For both needle layouts, a lower and more stable contact resistance is obtained as the overdrive distance is increased. Finally, a multicontact probing test is performed to evaluate the effect on the contact resistance of probe tip contamination following repeated surface contacts. The results show that the needles in the optimized layout are less heavily contaminated than those in the conventional layout, and hence the contact resistance is both lower and more stable. As a consequence, the probe card requires cleaning less frequently and hence its service life is improved.     

A highly simple failure detection method for electrostatic microactuators: application to automatic testing and accelerated lifetime estimation

Reliability and testability are two important factors for the development of batch fabrication of microelectromechanical systems (MEMS) or mixed MEMS/IC applications. In that frame, an easy-to-implement electrical method of detection of failures is presented in this paper, valid for every kind of electrostatic microactuators showing pull-in behavior, with great expectation value in the case of arrayed MEMS. The method relies on the detection of a pull-in current peak at very low frequency. An experimental setup is described and results are shown obtained with prototypes of electrostatic microactuators with parallel capacitances created by deep reactive ion etching on silicon-on-insulator wafers. This method is really suitable for automation and application to on-line testing during mass production and reliability studies. The functional schematic of a test circuitry is proposed for implementation in an industrial tester or for built-in self-test purposes. Then, in order to illustrate the benefits of this method for reliability studies, it is used in conjunction with high voltage testing for accelerated lifetime measurements. A time gain factor of 20 is achieved with above-mentioned test structures.     

Geometric design for ultra-long needle probe card for digital light processing wafer testing

The probe card with ultra-long probing needles is specifically designed for probe testing of wafers that feature protruding housing for digital micromirror devices (DMD) for digital light processing (DLP) applications. Compared with a conventional short probing needle, an ultra-long probing needle leaves a smaller scrub mark on the pad during probe testing but it suffers the risk from buckling. In this work, three-dimensional finite element models were developed and validated by experiments for single conventional and ultra-long probing needles to analyze their mechanical responses during wafer-level probe testing. Following the Taguchi method, we conducted separate optimal geometric designs for an ultra-long probing needle with respect to the minimized scrub length and minimized buckling potential. It was found that a long beam length of the ultra-long probing needle is preferred in reducing both scrub length and buckling potential. A compromised design that considers minimizing scrub length and buckling potential conjointly but with different weightings was presented.     

我国发展IC卡的措施

本文简述了ＩＣ卡的分类和性能，用对比的方法指出ＩＣ卡与磁卡的区别及ＩＣ卡的优越性。根据我国ＩＣ卡的发展现状，分析了当前制约ＩＣ卡发展的主要因素。并针对现状与存在的问题，提出了在我国发展ＩＣ卡应采取的和经营方式。     

Wafer-level packaging of silicon to glass with a BCB intermediate layer using localised laser heating

Adhesive wafer-level bonding is an excellent solution to meet the stringent requirements in micro-electro-mechanical systems (MEMS) packaging, one of the challenges in MEMS manufacturing, in a steadily growing micro-systems market. A range of bonding processes for commercially available substrate bonders have been developed, which apply global heating during the bonding procedure. This article, however, describes an approach where heating is kept to a minimum by combining the merits of laser joining, a truly localised heating technique, and adhesive wafer-level bonding. This unique bonding technique, which enables the use of temperature-sensitive materials within the package, is demonstrated for bonding of silicon to glass - materials commonly used in MEMS fabrication - with a benzocyclobutene (BCB) intermediate bonding layer. As a proof of concept for wafer-level packaging, bonding of two simplified patterns is demonstrated, one with five individual samples on the same wafer, and the other with nine samples. To verify the influence of this innovative bonding technique on the quality of the seal the devices are shear force tested and the results are compared with those of devices packaged at chip-level.     

非接触式IC卡硬件驱动层的功能测试方法

非接触式IC卡的应用日趋广泛,对嵌入式软件功能测试方法有效性与实用性提出了新的挑战。论文探讨了非接触式IC卡硬件驱动层的功能测试方法,包括在FPGA平台上进行在线测试以及样卡的回归测试方法。该文以嵌入式软件测试方法理论为基础,确定在进行硬件驱动层测试时可使用的功能测试方法,并依此设计测试用例;然后,确定样卡的回归测试方法;最后,根据测试环境以及实际项目情况,选择一种合适的测试架构。本文所提供的功能测试方法,可以有效地被利用在非接触式IC卡硬件驱动层的功能测试中。     

A wafer-level microcap array to enable high-yield microsystem packaging

Packaging represents a significant and expensive obstacle in commercializing microsystem technology (MST) devices such as microelectromechanical systems (MEMS), microopticalelectromechanical systems (MOEMS), microsensors, microactuators, and other micromachined devices. This paper describes a novel wafer-level protection method for MSTs which facilitate improved manufacturing throughput and automation in package assembly, wafer-level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized microcap array. This array consists of an assortment of small caps molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments associated with packaging. It may also include modifications which enhance its adhesion to the MST wafer or increase the MST device function. Depending on the application, the micromolded cap can be designed and modified to facilitate additional functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. The fabrication and materials selection of the microcap device is discussed in this paper. The results of wafer-level microcap packaging demonstrations are also presented.