Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

3D analytical modeling of surface potential,threshold voltage,and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage \((V_{\mathrm{T}})\) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on \(V_{\mathrm{T}}\) and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.     

Two-dimensional modeling of subthreshold current and subthreshold swing of double-material-gate (DMG) strained-Si (s-Si) on SGOI MOSFETs

The present paper proposes the surface potential based two-dimensional (2D) analytical models of subthreshold current and subthreshold swing of nanoscale double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The surface potential expression has been directly taken from our previous reported work. The effect of various device parameters on subthreshold current and swing like Ge mole fraction, Si film thickness, gate-length ratio and various combinations of control/screen gate work-functions have been discussed. The validity of the present 2D model is verified by using ATLAS^TM, a 2D device simulator from Silvaco.     

Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density \((Q_{inv} )\) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density \((Q_{inv} )\) has been equated to a threshold charge density \((Q_{th})\) in order to find the threshold voltage \((V_{th})\) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS.     

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by \({\sim }\)900 %), subthreshold swing characteristics (by \({\sim }\)12 %) and Drain Induced Barrier Lowering (DIBL) (by \({\sim }\)56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

A new two-dimensional analytical subthreshold behavior model for submicron Triple Material Gate (TM) GaN MESFET

A new two-dimensional (2D) analytical model for a Triple Material Gate (TM) GaN MESFET has been proposed and modeled to suppress the short channel effects and improve the subthreshold behavior. The analytical model is based on a two-dimensional analysis of the channel potential, threshold voltage and subthreshold swing factor for TM GaN MESFET is developed. The aim of this work is to demonstrate the improved subthreshold electrical performances exhibited by TM GaN MESFET over dual material gate and conventional single material gate MESFET. The results so obtained are verified and validated by the good agreement found with the 2D numerical simulations using the ATLAS device simulation software. The models developed in this paper will be very helpful to understand the device behavior in subthreshold regime for future circuit applications.     

Optimal design of the multiple-apertures-GaN-based vertical HEMTs with $$\hbox {SiO}_{2}$$ current blocking layer

Gallium nitride (GaN) based vertical high electron mobility transistor (HEMT) is very crucial for high power applications. Combination of advantageous material properties of GaN for high speed applications and novel vertical structure makes this device very beneficial for high power application. To improve the device performance especially in high drain bias condition, a novel GaN based vertical HEMT with silicon dioxide \((\hbox {SiO}_{2})\) current blocking layer (CBL) was reported recently. In this paper, effects of the thickness of CBL layer and the aperture length on the electrical and breakdown characteristics of GaN vertical HEMTs with \(\hbox {SiO}_{2}\) CBL are simulated by using two-dimensional quantum-mechanically corrected device simulation. Intensive numerical study on the device enables us to optimize and conclude that devices with \(0.5\hbox {-}\upmu \hbox {m}\)-thick \(\hbox {SiO}_{2}\) layer and \(1\hbox {-}\upmu \hbox {m}\)-long aperture will be beneficial considerations to improve the device performance. Notably, using the multiple apertures can effectively reduce the on-state conducting resistance of the device. On increasing the number of apertures, the drain current is increased but the breakdown voltage is decreased. Therefore, device with four apertures is taken as an optimized result. The maximum drain current of 84 mA at \(\hbox {V}_\mathrm{G}= 1\,\hbox {V}\) and \(\hbox {V}_\mathrm{D}= 30\,\hbox {V}\), and the breakdown voltage of 480 V have been achieved for the optimized device.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Silicene field effect transistor with high on/off current ratio and good current saturation

We investigate theoretically the possibility of exploiting the electrically tunable band gap property of silicene to achieve field effect transistor with improved characteristics. We find that the silicene field effect transistor where a band gap is introduced through a perpendicular electric field shows a subthreshold swing smaller than 60 mV/decade and a switching effect with high on/off current ratio exceeding \(10^{5}\). We find also that the device output characteristic displays a very good saturation due to improved pinch-off of the channel, stemming from the electrically induced band gap.     

A 3D analytical modeling of tri-gate tunneling field-effect transistors

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.     

A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs

The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50?nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.     

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ junction

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.     

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Impact of inelastic phonon scattering in the OFF state of Tunnel-field-effect transistors

We study the impact of electron–phonon interaction on the subthreshold operation region of Tunnel-FETs by means of full-quantum simulations. Our approach is based on the nonequilibrium Green’s function method, where acoustic and optical phonon scatterings are taken into account through the self-consistent Born approximation. Two device architectures are analyzed: InAs nanowire longitudinal Tunnel-FETs, and 2D vertical Tunnel-FETs based on either an GaSb/AlSb/InAs heterostructure or a MoS\(_2\)/WTe\(_2\) van der Waals heterojunction. In InAs nanowire Tunnel-FETs with interface traps, electron–phonon interaction deteriorates the subthreshold swing by allowing trap-assisted tunneling at energies higher than the valence-band edge in the source. In vertical heterojunction Tunnel-FETs, optical phonon scattering increases the OFF current by inducing inelastic transition in the overlap region even in the absence of traps.     

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.     

Asymmetric junctionless nanowire TFET with built-in $${n}^{+}$$ source pocket emphasizing on energy band modification

We present a detailed study on a technique to realize a narrow and highly doped built-in \({n}^{+}\) source pocket in an asymmetric junctionless nanowire tunnel field-effect transistor (AJN-TFET). In the proposed structure, a built-in \({n}^{+}\) source pocket is created between the \({p}^{+}\) source and the channel without the need for any separate implantation or epitaxial growth. This leads to band diagram modification by providing a local minimum in the conduction band which results in tunneling width reduction at the source–channel interface in on-state. This leads to an abrupt transition between on- and off-state, improved subthreshold swing (SS) (38 mV/dec), and significant on-current enhancement (\(\sim 2000\) times) at low operating voltage compared with the conventional TFET. We further study the effect of the length of the built-in \({n}^{+}\) source pocket on the AJN-TFET characteristics. The proposed structure overcomes the difficulty in creating a narrow \({n}^{+}\) pocket and thus renders the AJN-TFET device more amenable for the future scaling trend needed in low-power applications.     

Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance

In this paper, we aim to explore the potential benefits of using source side only dual-k spacer (Dual-kS) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low power operation at 20 nm gate length. It has been observed from the results that Dual-kS (inner spacer high-k) FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source side and results into improvement in transconductance \((g_{m})\) and output conductance \((g_{ds})\). It was also found that drain side only dual-k spacer (Dual-kD) improves the coupling of the gate fringe field to the underlap region towards the drain side which helps to shift away the drain field from gate edge and results into improvement in output conductance \((g_{ds})\) only at the cost of increase in Miller capacitance. A comparative simulation study has been performed on four different device structures namely both side low-k spacers (conventional), both side dual-k spacer (Dual-kB), Dual-kD and Dual-kS structures. From the simulation study, it was found that that Dual-kS structure has potential to improve \(g_{m}\) by \(\sim \)8.7 %, \(g_{ds}\) by \(\sim \)32.24 %, intrinsic gain \((A_{V0})\) by \(\sim \)11.44 %, early voltage \((V_{EA})\) by \(\sim \)47.59 %, maximum oscillation frequency (\(f_{MAX}\)) by \(\sim \)1.7 % and the ratio of gate-source capacitance and gate-drain capacitance \((C_{gs}/C_{gd})\) by \(\sim \)15.27 % with a slight reduction in the value of unity gain cut-off frequency (\(f_{T}\)) by \(\sim \)0.58 % in comparison to the conventional structure at drain current \((I_{ds})\) of \(10\,\upmu \)A/\(\upmu \)m. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on Dual-kS FinFET structure.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.