一种新型伪镜像滤波器组的实现方法

本文提出了一种新型２Ｍ个通道伪镜像滤波器组的结构和设计方法。本设计方法中，低通原型滤波器采用两级级联线性相位ＦＩＲ的结构，并使得整个分析／综合系统性能近于全恢复，无群时延失真。应用此方法设计伪镜像滤波器组，分析和综合滤波器组的结构和设计方法都比较简单，算法效率高，实现比较容易，这类滤波器组可用于语音的子带编码等。本文最后给出了一个实例。     

5G低轨卫星两步随机接入方案及其FPGA实现

为了实现低轨卫星通信系统高效率低时延的用户接入,提出了适用于低轨卫星系统的两步随机接入方案,对随机接入信道的数据发送、信道结构、前导码设计以及映射关系进行了设计,并进行了现场可编程门阵列（Field Programmable Gate Array,FPGA)实现。针对传统MAX-LOG-MPA算法FPGA处理时延长的问题,提出了一种节点并行迭代更新的FPGA接收机设计来降低处理时延。仿真结果验证了所设计的信道结构以及FPGA实现的可行性,相比传统接入方式可接入的用户数量更多,同时采用并行节点迭代更新的接收机将迭代处理时延降低为1/6。     

采用加权叠加结构滤波器组的子带分割与重构系统设计

子带分割与重构系统是天线组阵系统的重要组成部分。针对传统子带分割与重构系统参数设置不灵活的问题,提出了采用加权叠加(Weighted Overlap-Add,WOLA)结构滤波器组实现子带分割与重构的方法,对WOLA结构的分析滤波器组和综合滤波器组进行推导,利用窗函数法设计具有重构特性的原型低通滤波器,并利用Matlab进行仿真。仿真结果表明,采用WOLA结构子带分割与重构系统增强了参数设置的灵活性,当输入信号是理想无噪信号时,重构误差在5×10-3以内,与离散傅里叶变换(Discrete Fourier Transform,DFT)多相滤波结构相比,系统重构误差减小了一个量级;当输入带噪信号时,重构误差随着信噪比的增加而降低,当信噪比大于20 dB时重构误差回到5×10-3以内,验证了WOLA结构子带分割与重构系统的可行性和良好的重构特性。     

实时的 Gammatone听感知滤波器组的 FPGA实现

Gammatone听感知滤波器组能大幅度的提高数字助听器、语音增强和语音识别等语音处理系统的性能,但因其庞大复杂的计算量以及不可实时的综合方式限制了其实际应用。设计了一种高效的运算单元结构和复用架构,提出了一种通过延时补偿的方法简化其综合的方式,并在FPGA上实现了128通道的便于综合的可实时处理语音信号的Gammatone滤波器组。通过测试验证,该设计延时为20 ms ,满足实时性要求,能很好地重构语音信号,并提高语音增强系统的性能。     

过采样DFT滤波器组的一种简单设计方法

提出了一种几乎完全重构的过采样DFT调制滤波器组的设计方法.分析和综合滤波器组采用了不同的原型滤波器,使得设计自由度大为增加.考虑滤波器组的子带混叠、输出混叠、系统失真要求,推导并给出了相应的设计算法.实验结果证明提出的方法在相同滤波器长度情况下可以得到更好的阻带衰减.     

群时延内均衡的模拟滤波器优化设计

为解决滤波器幅频特性算术对称性和通带内群时延波动之间的矛盾,提出了一种滤波器群时延内均衡优化设计方法,即在网络综合法设计的滤波器电路基础上,将电路与时延均衡器直接耦合,用最小二乘法使群时延特性逼近一个常数,然后利用无约束优化算法对整个电路进行优化来降低通带内群时延波动.仿真结果表明,该方法不但能使滤波器幅频特性算术对称...     

A Modular Design of LMS Adaptive Filter Based on FPGA

针对LMS自适应滤波器在FPGA上实现结构灵活性的问题,提出了一种模块化设计方法。根据LMS算法结构特点,结合FPGA硬件语言特点进行模块化设计,分别阐述了各模块设计结构,对模块进行并行调用与综合。对模块化设计的自适应滤波器与纯串行及纯并行设计的自适应滤波器所占用的资源以及处理速率进行比较,8个并行模块结构比全串行结构处理速率快了近7.6倍,硬件资源占用比全并行结构减少了近50%;结果说明模块化LMS自适应滤波器设计具有更加灵活的结构特点。     

基于FPGA的高速并行滤波器设计与实现

针对高速通信调制解调系统对成形滤波器的运算要求,分析高速并行滤波器的设计与实现方法,提出一种可满足 1Gsps 符号速率下的发射端和接收端的成形滤波器并行实现结构, 该结构具有较低的实现复杂度。FPGA 实现结果表明,采用该滤波结构的高速调制解调系统基本没有性能损失。     

基于多速率DA的根升余弦滤波器的FPGA实现

根升余弦滤波器的传统实现结构占用的FPGA逻辑资源较多,针对一个特定的多速率系统的实现,首先采用多速率处理技术,较少计算量,针对多速率系统中的48阶根升余弦滤波器,采用分布式算法,并结合流水线技术,提出了基于FPGA的实现方案.与传统结构实现的滤波器相比达到了提高资源利用率、提高系统工作频率以及提高计算速度的目的.和Quartus Ⅱ中IP core实现的滤波器相比,最大工作频率低但占用资源少.     

多相并行FIR滤波器的FPGA高速实现方法

L路多相并行FIR滤波器的工作速率是单路串行FIR滤波器的L倍,基于多项式分解的多相并行FIR滤波器实现结构简单、计算复杂度小、滤波运算延迟少;针对多相并行FIR滤波器,给出了基于多项式分解的多相并行FIR滤波器优化实现结构的FPGA高速实现方法。归纳、整理和推导了2路至8路基于多项式分解的多相并行滤波器优化实现结构,并针对FPGA实现的具体特点给出了多相并行滤波器优化实现结构的FPGA高速实现方法。通过测试分析可知,给出的基于多项式分解的多相并行FIR滤波器优化实现结构的FPGA高速实现方法能够在FPGA上高速实现多相并行FIR滤波器。     

Design of M‐Channel IIR Uniform DFT Filter Banks Using Recursive Digital Filters

In this paper, we propose a method for designing a class of M‐channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop‐band attenuation, which is also taken care of in the proposed algorithm.     

一种最优去噪线性相位滤波器组的FPGA实现

格型结构是一种可以快速高效设计过采样线性相位完全重建滤波器组的方法。一旦分析滤波器组设定后,对应的综合滤波器结构也就确定,但综合滤波器组参数却有很大的灵活性,从中可以找出具有最优去噪效果的综合滤波器组,构成一个完整的滤波器组。对于求解出的具有最优去噪效果的过采样线性相位完全重构滤波器组,文中用DSP Builder在FPGA上予以实现,并用modelsim进行功能仿真。     

An efficient digital implementation of multicarrier CDMA system based on generalized DFT filter Banks

In this paper, an efficient digital implementation of multicarrier transmission scheme based on generalized discrete Fourier transform (DFT) filter banks is presented for multicarrier code-division multiple-access (MC-CDMA) systems. Generalized DFT filter banks has been traditionally discussed for very high-speed digital subscriber lines (VDSL) wireline systems, received interest also for wireless applications. The design of the generalized DFT modulated filter banks is investigated and its fast implementation is derived in the time-domain for arbitrary integer sampling rate. Through the utilization of the generalized DFT modulated filter banks, one or more subcarriers, even noncontiguous subcarriers can be easily supported by system in both uplink and downlink, which facilitates the users to access the network in a frequency-division multiple-access manner. Simulation results show that the overall bit-error-rate performance of the proposed multicarrier transmission scheme well approaches that of a single-carrier system due to the negligible intercarrier interference introduced by an appropriate design of the generalized DFT modulated filter banks.     

An Efficient FPGA-based Implementation of Fractional Fourier Transform Algorithm

In this paper, we present an efficient FPGA implementation method of fractional Fourier transform (FrFT) algorithm. Firstly, a polyphase implementation of the FrFT computation algorithm base on the theory of multirate signal processing and filter banks is proposed. This polyphase implementation costs less computations and its parallel structure is suitable for FPGA realization. Then we present one computational method, which improve the resolution on any portion of fractional spectrum. Some realization details, such as the parity restrictions of signal length, special interval for transform order, interpolation filter, continuous frame computation and continuous order computation are also investigated. Finally, the efficiency of the novel method is verified by FPGA implementation results.     

Reconfigurable Multiplier Blocks: Structures,Algorithm and Applications

This paper presents the efficient design methodology and applications of reconfigurable multiplier blocks (ReMB). ReMB offers significant area, delay and possibly power reduction in time-multiplexed implementation of multiple constant multiplications in many application areas from fixed digital filters, adaptive filters, and filter banks to DFT, FFT and DCT. The reader will be exposed to the fundamental principles of ReMB structures coupled with a novel algorithm for their design as well as illustrative examples where appropriate that help the reader understand the technique in action. The paper also looks into the pros and cons of deploying the technique on standard FPGA platforms as well as discussing the effectiveness of the ReMB approach in custom silicon realization by means of application examples. Area, delay and power (where possible) of the ReMB designs are compared to standard implementations. S.S. Demirsoy now with Altera European Technology Centre, High Wycombe, UK. A. Dempster now with the School of Surveying and Spatial Information Systems, University of New South Wales, Sydney, Australia.     

Design of stable, causal, perfect reconstruction, IIR uniform DFTfilter banks

Design procedures for stable, causal and perfect reconstruction IIR parallel uniform DFT filter banks (DFT FBs) are presented. In particular a family of IIR prototype filters is a good candidate for DFT FB, where a tradeoff between frequency selectivity and numerical properties (as measured by the Weyl-Heisenberg frames theory) could be made. Some realizations exhibiting a simple and a massively parallel and modular processing structure making a VLSI implementation very suitable are shown. In addition, some multipliers in the filters (both the analysis and synthesis) could be made; powers or sum of powers of 2, in particular for feedback loops, resulting in a good sensitivity behavior. For these reasons as well as for the use of low order IIR filters (as compared with conventional FIR filters), the overall digital filter bank structure is efficient for high data rate applications. Some design examples are provided     

基于FPGA的多分辨图像融合系统实时实现的研究

文章在分析了主流的Laplacian金字塔多分辨图像融合算法处理特点的基础上，介绍了基于FPGA的实时实现方法，给出了滤波、插值、延时、融合等算法模块的参数化设计方案及其并行处理流水线的细分和优化技术，分析了各个模块的资源占用情况，可以在单片Xilinx V4SX35 FPGA上实现双通道720×576×10bit图像的3层Laplacian金字塔算法融合处理。实验结果显示，采用该方法设计的融合系统融合效果良好，处理延迟小，可以实现25f/s的实时融合处理。     

Multidimensional multirate filters and filter banks derived fromone-dimensional filters

A method by which every multidimensional (M-D) filter with an arbitrary parallelepiped-shaped passband support can be designed and implemented efficiently is presented. It is shown that all such filters can be designed starting from an appropriate one-dimensional prototype filter and performing a simple transformation. With D denoting the number of dimensions, the complexity of design and implementation of the M-D filter are reduced from O(N^D) to O(N). Using the polyphase technique, an implementation with complexity of only 2N is obtained in the two-dimensional. Even though the filters designed are in general nonseparable, they have separable polyphase components. One special application of this method is in M-D multirate signal processing, where filters with parallelepiped-shaped passbands are used in decimation, interpolation, and filter banks. Some generalizations and other applications of this approach, including M-D uniform discrete Fourier transform (DFT) quadrature mirror filter banks that achieve perfect reconstruction, are studied. Several design example are given     

Designs and architectures of filter bank trees for spectrally efficient multi-user communications: review, modifications and extensions of wavelet packet filter bank trees

A review is presented first of the evolution of transmultiplexers since about 1966, in the context of a long progression of theoretical advances and developments leading to recent proposals to fundamentally improve OFDM type systems using principles of perfect reconstruction filter (PRF) banks. The equivalence of transmultiplexers to OFDM type multi-user systems is discussed. The desirable goals for performance and implementation of transmultiplexers or multiband, multiuser communication systems that are addressed and met in this paper using filter bank trees are set down. Then modifications and extensions are presented of the designs and architectures of wavelet packet based synthesis and analysis pairs of filter bank trees (Sablatash and Lodge in Digital Signal Process 13: 58–92, 2003) that can be used as transmultiplexers. These exhibit a number of advantages over the previous designs and address three shortcomings of the designs used to illustrate basic principles in Sablatash and Lodge (Digital Signal Process 13:58–92, 2003). The first of these is the asymmetry of the magnitude frequency responses of the multiplexer channels, which is addressed using a symmetric design for a lowpass and highpass quadrature mirror filter (QMF) pair described herein. The second is the problem of minimizing the total delay of the signal in passing through the analysis and synthesis filter banks. This is addressed using an architecture involving DFT polyphase synthesis filter banks to replace the wideband VSB filters at the roots of the two identical synthesis filter bank trees, but results in the multiplexer having fewer levels. In this way a tradeoff is effected of lower delay and complexity with fewer levels of bandwidth on demand. At the receiver matching DFT polyphase analysis filters and the other matching analysis filters are implemented. The third shortcoming is the difficulty in designing a synchronization scheme if the filters in the synthesis and analysis filter banks have non-linear phase. This is addressed by designing linear phase filters that do not affect the ISI to any significant degree for communication purposes, although exact perfect reconstruction is lost, but greatly ease and improve the design of the synchronization scheme. Relationships of this paper and its advantages over recent research studies and IEEE 802.22 standards proposals using PR filter banks for multi-user systems to greatly improve on OFDM systems are discussed. Financial support under Industry Canada’s Spectrum Research Funding is gratefully acknowledged.     

针对级联型ⅡR滤波器群延时的均衡优化技术

为了减小由非恒定群延时所引起的滤波器的输出信号失真,本文提出一种适用于级联型无限长脉冲响应数字滤波器的群延时均衡优化方法.通过在级联型ⅡR数字滤波器每一级的输出插入全通均衡器,减小群延时在通带范围内的变化,进而减小滤波器的输出信号失真.对于本文提出的群延时优化方法,当采用1阶和2阶均衡器进行电路优化时,在0~100Hz的通带范围内,分别将群延时的变化量减小了28.19%和49.93%.基于0.18μm CMOS标准单元库进行逻辑综合与版图设计,最终得到整个滤波电路IP核版图的面积为0.1747mm².相比于已有文献方法,本文方法在群延时优化上效果显著,电路实现上功耗和面积较小,非常适合片上系统应用.