新型相位式激光测距系统电路的设计

为了提高相位式激光测距系统的精度和可靠性,设计了一种新型的相位式激光测距系统的发射和两路几乎一致的接收电路。通过采用具有微小频差的低抖动时钟发生技术,差频测相技术等原理,系统可以实现特定环境下的高精度测量。系统由级联式PLL可编程时钟信号源、激光发射与接收模块、自动增益控制、混频滤波及数据采集组成。利用时钟源产生调制信号,并对反馈信号和接收信号进行放大、混频滤波等信号调理,进而采集数据并对数据进行处理分析。在电路的设计中,优化了激光的调制发射电路,采用低回波损耗的尾纤式激光器,增加简单实用的自动增益模块等。实验观察的波形和数据结果分析表明,此相位式激光测距系统电路简单实用,并且具有较高的稳定性和较高的测量精度。     

光纤光栅传感器阵列化与温度补偿研究

利用啁啾光纤Bragg光栅（FBG）反射和长周期FBG边沿滤波，提出并实现了一种综合的FBG传感快速解调方案。封装1对FBG进行应变差动传感、同时消除温度影响，不增加波长资源占用并使应变灵敏度得到有效提高，温度影响在很大范围内几乎为0。在全光纤化解调温度补偿型传感的基础上，研究了两路时分复用的设计方法，给出了时分链路间延迟光纤与光脉冲和解调端时分选通门的关系，实验结果与理论分析吻合。     

基于非线性滤波器的FBG解调系统的研究

传统的光纤Bragg光栅(FBG)滤波解调系统解调精度 较低,且线性滤波器的滤波曲线不是严格 的线性。从理论推导了基于线性滤波器的解调系统中滤波光和直接探测光光功率的比 值和滤波器的 透过率函数成正比。而传统的线性滤波解调方法过于理想化,为了修正这一问题,根据理论 推导对波长和 比值的关系按非线性滤波解调处理。实验结果表明,非线性解调 系统的温度解调精度高于线性解调系统,一定程度上提高了解调系统的精度。而且线性滤波 器的FBG解调 系统中几乎全部采用实际波长进行解调,本文在非线性滤波解调系统中引入虚拟波长的概念 ,对基于线性 滤波系统或非线性滤波系统的FBG系统进行解调,从而可以不用对实际波长的变化进行标定 而直接解调出FBG所处环境温度的变化。     

基于F-P滤波器的多波长时钟提取

提出一种简单的全光单一链路的多波长时钟同时提取方案。利用Fabry-Perot(F-P)滤波器对波分复用(WDM)系统中多波长的归零(RZ)码信号进行时钟提取,滤波器后面接半导体光放大器(SOA)对F-P滤波器提取出的时钟进行整形处理,通过实验证实了用F-P滤波器对两路不同波长的10 Gbps信号时钟提取的可行性以及同一SOA同时处理双波长时钟的能力,两路提取时钟的单边带相位噪声分别达到-82.815和-83.072dBc/Hz@10 kHz。     

一种基于反射式SOA的FBG传感解调方法

提出一种基于反射式半导体光放大器（R-SOA）的光纤Bragg光栅（FBG）传感解调方法。周期性调谐R-SOA与可调谐FBG构成的窄带可调谐激光器,当其输出波长与FBG传感器反射波长一致时,由光电探测器输出光电流最大判断2个FBG周期的匹配并完成对传感FBG周期的测量。测量结果表明,FBG传感器中心波长在1 551.9...     

三角形谱啁啾光纤光栅在光栅传感系统中的应用

利用三角形谱啁啾光纤布拉格光栅（T-CFBG）的反射和时延特性，提出了一种新的基于相位检测的FBG解调方案。该方案由光强来确定传感器光栅反射波长的相位延迟角范围，由相位检测来确定在该范围的相位延迟角大小，两者结合给卅传感光栅的反射波长，因此具有更高精度和更大波长检测范围。实验制作了宽带宽具有三角形反射谱的T-CFBG，并对其用于传感解调予以了模拟分析。     

光纤光册中光弹效应的研究

在使用相位掩模板技术写入光纤光栅（FBG）时，观察到，当夹固光纤的张力不一样时，光栅写入时所监视到的布喇格波长也不一样，利用这种现象，直接探测了FBG中的光弹效应，通过对实验数据的分析计算发现，光纤的有效应变光系数不是常数，而是随着光纤轴向应变的增大而略微增大，这和通常的说法不一样。     

光纤布拉格光栅的高温特性研究

采用相位掩模法制作的掺Ge石英光纤布拉格光栅(FBG)作为实验对象,监测FBG从30℃到850℃谐振波长随环境温度的变化,研究FBG的高温特性。实验结果表明,FBG处于30℃～690℃时,其谐振波长与温度间有良好的线性关系;随着温度的升高,FBG的谐振波长温度关系开始偏离其原有的线性;在温度达到837℃时,FBG的光栅特性消失;如果FBG工作在失效温度范围以内,则FBG具有良好的重复性。通过分析研究,提出了用原子弹性模型解释FBG在高温状态下失效原因的新观点。     

基于高精细度F-P滤波器的40Gb/s全光时钟提取

提出了一种基于高精细度Fabry-Perot(F-P)滤波器的全光时钟提取方案,并进行了实验验证。为了实现对信号波长无关的特性,系统利用光纤中交叉相位调制(XPM)效应对输入信号进行正码波长变换,使变换后的波长始终与F-P滤波器的透射峰精确对准。采用精细度为1 012的高精细度F-P滤波器提取时钟,并利用半导体光放大器(SDA)的自增益调制(SGM)效应进一步抑制时钟信号的低频噪声,保证了高质量的时钟输出。实验中,利用这种装置对40 Gb/s归零(RZ)码信号进行了时钟提取,得到了抖动为285 fs的高质量40 GHz时钟信号,验证了方案的可行性。     

光纤Bragg光栅滤波响应的轴向分布特性研究

为揭示光纤Bragg光栅（FBG）的局部滤波特征,研究和分析了滤波响应沿光栅轴向的空间分布规律。从均匀、切趾和啁啾型等基本光纤Bragg光栅（FBG）类型出发,分析了反射带滤波光场沿轴向的分布规律。结果表明,均匀型FBG中,光场反射多集中在前1/2个光栅长度内,呈现非对称性;切趾型FBG中,光场反射在光栅长度内的均匀性...     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

基于DLL的1.25G超宽带通信系统时钟生成电路

设计并实现了一个基于延时锁定环(DLL)、用于超宽带(UWB)无线通信系统的1.25GHz时钟生成电路。该时钟生成电路由两个DLL和一个自调谐LC滤波电路组成,输入125MHz的参考时钟,输出1.25GHz的差分时钟和间隔100ps的16相时钟。通过优化电荷泵电路有效地减小了静态相位误差,新式自调谐LC滤波电路的应用消除了工艺偏差对谐振的影响。在1.8V电源电压,SMIC0.18μmCMOS工艺下,该时钟生成电路在各种工作条件下均表现出良好的性能,在标准情况下静态相位误差仅为9ps,最大时钟抖动为10ps。当电感存在30%的工艺偏差时,滤波电路的谐振频率能够自动维持在1.25GHz上。     

A 10 Gb/s ATM data synchronizer

Asynchronous transfer mode (ATM) data comes from different sources, and it is by nature bursty, hence causing the incoming phase and exact bit rate to vary from burst to burst. In order to retime the bursty data, a conventional yet low-Q clock recovery scheme could be used, but the downstream system components would have to cope with the consequent clock interruptions and variations in phase and frequency. This work presents a phase agile data synchronizer integrated circuit that retimes bursty ATM cells at 10 Gb/s to an external 10 GHz clock. The integrated circuit comprises an analog variable data delay, a phase detector, an edge detector, a loop filter, and a data retime. It has a total delay range of 200 pS. The integrated circuit has been fabricated in both AlGaAs/GaAs and InGaP/GaAs HBT technology     

A second-order semidigital clock recovery circuit based on injection locking

A compact (1 mm /spl times/ 160 /spl mu/m) and low-power (80-mW) 0.18-/spl mu/m CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscillator output can have its output clocks interpolated by current steering the injecting clocks. A second-order clock and data recovery is introduced to perform the interpolation and is capable of tracking frequency offsets while exhibiting low phase wander.     

A Phase Interpolator CDR with Low-Voltage CML Circuits

In this paper, a phase interpolator clock and data recovery (CDR) with low-voltage current mode logic (CML) latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.     

First-order PMD monitoring for NRZ data using RF clock regeneration techniques

We propose and demonstrate two novel techniques for 10 Gb/s polarization-mode-dispersion (PMD) monitoring for NRZ signals that use a regenerated RF clock tone as a monitoring signal. Our techniques regenerate the RF clock tone that is usually absent after square-law detection in the electrical NRZ data spectrum (in the absence of dispersion). Our first technique uses a dispersive element in the monitoring tap-line to put the beat terms between the optical clock sidebands and the carrier in phase and thus regenerates the RF clock tone after detection. Our second technique involves the use of an optical filter that is centered at the bit rate frequency on either the upper or lower sideband of the optical spectrum, removing one of the sidebands and thus preventing the beating that normally cancels the RF clock tone. We show (theoretically, via simulation, and experimentally) the effect that PMD has on these regenerated RF clock tones. We also demonstrate PMD compensation at 10 Gb/s using these techniques for monitoring and show a 6-dB improvement in the 1% power penalty tail. Our techniques are simple, do not require modification at the transmitter, and can be applied to WDM systems via the use of a multichannel dispersive element or a tunable filter swept across all channels.     

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator

A 2.5 Gb/s burst-mode clock and data recovery (CDR) circuit is presented that uses a 1/8th-rate ring oscillator with two pulses running simultaneously that are phase independent. One “tune” pulse sets the delay of the ring by phase locking it to a reference. The other “clock” pulse tracks the phase of the incoming data by a process of pulse removal and reinsertion. Because both pulses share the same ring, there is no frequency mismatch between the incoming data stream and the recovered clock in frequency synchronous systems, allowing for large data run lengths. A 1:8 data-demux clock is naturally generated by tapping the clock pulse along the ring. Phase acquisition is instantaneous from a single data edge. Run length tolerance is larger than 72 bits. The 0.6 mm$^{2}$ 0.13 $mu$m CMOS chip includes a CML-to-CMOS input buffer, PLL with on-chip loop filter, PRBS checker, 1:8 data demux, and eight output buffers. It has 2.7 ${rm UI}_{rm pp}$ measured jitter tolerance at 100 kHz and consumes 42 mW from a single 1.2 V supply.      

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

Investigation of a Rate-Selectable All-Optical Packet Clock Recovery System

This letter presents the experimental performance of a rate-selectable all-optical packet clock extractor using a Fabry-Perot (F-P) filter, a semiconductor optical amplifier (SOA), and polarization interferometers (PIs). The F-P filter with a low finesse and a free-spectral range (FSR) equal to the lowest packet data rate was used to directly extract the packet clock from the packet data stream, which ensures that the clock locks fast and vanishes quickly. Different PIs, in conjunction with the F-P filter, were used to form comb filters with different FSRs in order to suppress the undesired subharmonic frequencies. The clock then goes into SOA to reduce the low-frequency amplitude noise. We demonstrate packet clock extraction at 10, 20, and 40 Gb/s with the combination filter.