2.4GHz 0.35-μm CMOS全集成线性功率放大器设计

片上系统射频功率放大器是射频前端的重要单元.通过分析和对比各类功率放大器的特点,电路采用SMIC0.35-μm CMOS工艺设计2.4 GHz WLAN全集成线性功率放大器.论文中设计的功率放大器采用不同结构的两级放大,驱动级采用共源共栅A类结构组成,输出级采用共源级大MOSFET管组成.电路采用SMIC 0.35-μ...     

基于GaN TMIC集成片上天线技术的太赫兹功率放大器

介绍了一种由矩形微带贴片天线和功率放大器一体化集成设计的发射类型单片太赫兹集成电路.该电路采用 GaN HEMT 工艺制备, 实现了高功率密度和高效集成.片上天线被设计为功率放大器输出端接的功率辐射器和频率相关的输出负载调谐器.采用负载牵引技术实现了放大器与天线之间良好的阻抗匹配.在 100~110 GHz的频带范围内, 功率放大器的平均输出功率为 25.2 dBm, 平均功率附加效率（PAE） 为5.83%.单片太赫兹集成电路具有良好的辐射特性, 芯片的10 dB带宽为 1.5 GHz, 在109 GHz估算的等效各向同性辐射功率 （EIRP） 为 25.5 dBm.     

基于GaN TMIC集成片上天线技术的太赫兹功率放大器（英文）

介绍了一种由矩形微带贴片天线和功率放大器一体化集成设计的发射类型单片太赫兹集成电路.该电路采用GaN HEMT工艺制备,实现了高功率密度和高效集成.片上天线被设计为功率放大器输出端接的功率辐射器和频率相关的输出负载调谐器.采用负载牵引技术实现了放大器与天线之间良好的阻抗匹配.在100～110 GHz的频带范围内,功率放大器的平均输出功率为25.2 dBm,平均功率附加效率(PAE)为5.83%,单片太赫兹集成电路具有良好的辐射特性,芯片的10 dB带宽为1.5 GHz,在109 GHz估算的等效各向同性辐射功率(EIRP)为25.5 dBm.     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

基于有源匹配转换器的全集成双频带射频CMOS功率放大器的设计

设计了基于有源转换器的双频带射频CMOS功率放大器,该放大器可以应用于移动WiMAX系统.设计采用了0.13μmCMOS工艺并且所有的匹配完全集成在芯片内.转换器可以通过有源匹配而在双频带工作,在2.5和3.5GHz,转换器的效率为78.2%和70.4%,功率放大器的增益分别为26.5和24.8dB,功率增加效率为20%和28%,在平均功率25dBm处,三阶交调系数均低于-30dBc.     

一种0.18μm全集成锗硅BiCMOS功率放大器设计

本文提出了一种用于多模前端集成电路的全集成功率放大器,该功率放大器采用0.18μm锗硅BiCMOS工艺设计,所有匹配网络及元件全部片上集成。利用负载牵引测试技术,得到了最佳功率放大级器件尺寸,并对版图进行了优化,最终的测试结果显示：该功率放大器在2.4GHz处最大输出功率达到24dBm,在5dBm功率输入时,得到输出1dB功率压缩点,为21dBm,此时功率附加效率为18%。该功率放大器全部片上测试,没有任何邦定线及片上匹配,可用于多模片上系统的功率模组集成。     

基于有源匹配转换器的全集成双频带射频CMOS功率放大器的设计

设计了基于有源转换器的双频带射频CMOS功率放大器,该放大器可以应用于移动WiMAX系统. 设计采用了0.13μm CMOS 工艺并且所有的匹配完全集成在芯片内. 转换器可以通过有源匹配而在双频带工作,在2.5和3.5GHz,转换器的效率为78.2%和70.4%,功率放大器的增益分别为26.5和24.8dB,功率增加效率为20%和28%,在平均功率25dBm处,三阶交调系数均低于-30dBc.     

解决电源与EMI问题D类功率放大器优势显现

目前包括高度集成设备以及将调制器与输出级分开的多芯片技术在内的电路拓扑规则已经大量出现.D类功率放大器的出现,使音频放大器的功率效率由原来的30%～50%急剧增加了近两倍,达到了85%～90%,除此之外,也使器件壳体的体积大幅缩小,D类功率放大器原理图如图1.D类功率放大器采用了多芯片技术,在输出级与电源端需要改变时,相同的设计方法可以移植到不同的功率放大系统中.     

S波段小型管壳封装高增益高可靠功率放大器的设计

基于功率放大器模块化、小型化的发展需求,设计了一种S波段小型管壳封装、高增益、高可靠线性功率放大器,采用微波薄膜混合集成电路工艺,双电源供电,将三级放大电路一体化集成到全密封金属管壳,阐述了功率放大器的高增益、高可靠、小体积设计.测试结果表明放大器功率增益29 dB,1 dB输出功率大于34 dBm,功率附加效率大于38%,70℃壳温功率管芯结温101℃,外形尺寸13mm×21mm×5.5mm.技术指标满足设计要求,可靠性满足Ⅰ级降额设计.     

用两片LM3886实现输出电流及功率扩展的方法

随着大规模集成电路的发展，传统的由分离元件组成的功率放大器正在被高度集成化的功率模块所代替。尤其在输出功率为20～50W之间的功率电源和标准源的设计当中，许多生产厂家在功率输出级均采用了先进的大规模集成功放，这既节约了成本，又缩短了电路调试周期，同时增强了仪器的可靠性，对产品的规模化和标准化生产带来很大的益处，因此大规模集成功率放大器在功率放大器设计中已成为设计者的第一选择，应用前景越来越广阔。     

Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.     

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8.     

Transformer-coupled cascode stage for mm-wave power amplifiers in sub-μm CMOS technology

An amplifier topology based on a transformer-coupled cascode stage is presented and compared with the most used solutions for sub-μm CMOS power amplifiers, which are the common-source stage, cascode stage, and capacitive-coupled cascode stage. The comparison was carried out by designing each amplifier in a 65-nm CMOS technology and for a 60-GHz operating frequency. The design was optimized for a trade off among power gain, saturated output power, and linearity. Operating from a 1.2-V supply voltage, the proposed amplifier improves both small-signal and large-signal performance with respect to the most common approaches, thus demonstrating effectiveness with sub-μm CMOS technologies and mm-wave operation.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

A CMOS logarithmic IF amplifier with unbalanced source-coupledpairs

A CMOS logarithmic intermediate-frequency (IF) amplifier that is applied to mobile telecommunications equipment is presented. The CMOS logarithmic IF amplifier has pseudologarithmic rectifiers made from parallel-connecting full-wave rectifiers, consisting of unbalanced source-coupled pairs with the cross-coupled input stage and parallel-connected output stage. A ±3-dB logarithmic accuracy, a 90-dB input dynamic range, and a -30 to 80°C operating temperature range were achieved with the 1.3-μm double-polysilicon n-well CMOS process. Typical power consumption by the logarithmic IF amplifier in the fabricated CMOS LSI was 5.5 mW. The block area for the logarithmic IF amplifier was 0.8 mm²     

A 1.8-GHz CMOS Power Amplifier Using a Dual-Primary Transformer With Improved Efficiency in the Low Power Region

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.     

A CMOS RF Polar Transmitter of a UHF Mobile RFID Reader for High Power Efficiency

A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860–960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-$mu$ m CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.      

CMOS工艺射频功率放大器的实现与验证

射频功率放大器是无线设备的关键器件,GaAs工艺被广泛使用在射频功放的设计制造上。而CMOS工艺在生产成熟度和成本上有很大优势,主要关注用CMOS工艺来做射频功放的问题,介绍世界上第一颗量产的CMOS功放及其所使用的特殊技术。利用一款成熟的手机产品,替换这颗功放及外围器件,最后与原产品进行对比测试。     

A CMOS differential buffer amplifier with accurate gain andclipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques