A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.     

On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs     

Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors

The subthreshold radio-frequency (RF) characteristics of multi-finger nanoscale MOS transistors were studied by using the measured scattering (s) parameters. Small-signal circuit parameters were determined based on a simplified small-signal equivalent circuit model. We found that besides the source and gate resistances, most of the parameters such as the channel resistance, drain inductance and intrinsic capacitance are found to be significantly different to those in the saturation mode of operation. The subthreshold channel resistance increases and the drain inductance decreases as the finger number increases because of the more significant charge transport along the finger boundaries. In addition, the channel resistance can be governed by the drain-induced barrier lowering in a transistor with very short gate length. The equivalent intrinsic capacitance of the small-signal equivalent circuit is governed by the substrate resistance and capacitance which make the parameter extraction more difficult.     

A generalized MoM-SPICE iterative technique for field coupling to multiconductor transmission lines in presence of complex structures

A generalized method of moments (MoM)-SPICE iterative technique for field coupling analysis of multiconductor transmission lines (MTLs) in the vicinity of complex structures is presented. Telegrapher's coupling equations are modified with additional distributed voltage and current sources for more accurate analysis of the total current induced onto transmission line bundles in the presence of complex structures. These additional voltage and current sources are introduced to enforce the electric field boundary condition and continuity equation on MTLs beyond the quasi-static regime. The surrounding structure is modeled via the MoM and a SPICE-like simulator is used to simulate equivalent circuit model of the MTLs extracted via the partial element equivalent circuit method. The proposed technique is based on perturbation theory with the quasi-static current distributions on the transmission lines still assumed to be dominant. Validation examples for single and MTLs are given in the presence of complex structures.     

Analytical parameter extraction of the HBT equivalent circuit withT-like topology from measured S-parameters

A pure analytical method for extraction of the small-signal equivalent circuit parameters from measured data is presented and successfully applied to heterojunction bipolar transistors (HBT's). The T-like equivalent circuit is cut into three shells accounting for the connection, and the extrinsic and intrinsic parts of the transistor. The equivalent circuit elements are evaluated in a straightforward manner from impedance and admittance representation of the measured S-parameters. The measured data are stripped during the extraction process yielding, step by step, a full set of circuit elements without using fit methods. No additional knowledge of the transistor is needed to start the extraction process with its self-consistent iteration loop for the connection shell. The extrinsic and intrinsic equivalent circuit elements are evaluated using their bias and frequency dependencies. This method yields a deviation of less then 4% between measured and modeled S-parameters     

Extraction of the InP/GaInAs heterojunction bipolar transistorsmall-signal equivalent circuit

An extraction technique for determining the small-signal equivalent circuit model of an InP/GaInAs heterojunction bipolar transistor is presented. The equivalent circuit includes the extrinsic base collector capacitance and extrinsic base resistance. It is clearly indicated which elements are uniquely determined, and which elements are estimated     

High-frequency network properties of MOS transistors including the substrate resistivity effects

The small-signal differential equations describing the intrinsic high-frequency characteristics of MOS transistors are derived under three basic modes of signal application: gate excitation, substrate excitation, and combined gate-substrate excitation. These equations are shown to be analogous to those of a double RC transmission line having a uniformly distributed common resistance but two separate capacitances distributed nonuniformly. High-frequency device admittances are calculated in terms of those of the analog RC transmission line using the method of "piecewise" uniformity for the capacitance distributions. Useful expressions are derived for the various Y-parameters which are explicitly related to the more readily measurable low-frequency input capacitance and transconductance parameters which, in turn, are related to the basic device physical parameters. The admittance expressions clearly indicate the influence of the substrate resistivity both on the forward transfer admittance magnitudes at low and high frequencies and on the input conductance at high frequencies. The intrinsic Y-parameters are combined with the associated extrinsic RC networks and presented in the form of equivalent circuits. Results of UHF admittance measurements on representative n-channel devices are given which support the overall validity of the proposed equivalent circuit models.     

MOS transistor modeling for RF IC design

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-μm CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement     

A New Approach for SOI Devices Small-Signal Parameters Extraction

SOI devices are frequently used nowadays in the RF and HF field. Design of complex SOI integrated circuits involves a prior detailed analog simulation, that can only be performed through accurate SOI active components models. We are interested here in linear operation modeling; we test new methods for small-signal parameters determination, suitable for a conventional MOSFET high-frequency model and somewhat inspired from methods applied to MESFET technology. In this paper, we deal mainly with extrinsic parameters, for which we obtain reliable estimation on a large frequency range. Our finally adopted extraction procedure takes closely into account the model topology, which reflects the device electrical behavior. We completely describe the procedure, from measurements to the extracted equivalent circuit simulation, without having to optimize parameters and with a straightforward extrinsic elements extraction.     

Validation of the sub-circuit modelling approach for substrate resistance in 0.13 μm RF MOSFETs

Great progress has been made on modelling the behaviour of deep-submicron MOS devices, especially concentrating on the performance and operation of the intrinsic device structures. To properly represent the RF performance of these devices, the extrinsic structure must also be considered and a variety of sub-circuit configurations, especially for the substrate, have been proposed. As the frequency of operation rises, it may be expected that more elaborate multi-element substrate sub-circuits will become necessary. Here, we consider the RF operation of advanced 0.13 μm NMOS transistors up to 10 GHz and demonstrate that a simple sub-circuit, using only a single resistor, allows accurate simulation of the two-port parameters, including y ₂₂. We thus demonstrate that the single-resistor substrate sub-circuit approach remains a simple, yet valid, modelling option for MOS simulation up to 10 GHz.     

An extrinsic-inductance independent approach for direct extractionof HBT intrinsic circuit parameters

A novel analytical procedure has been proposed for direct extraction of the intrinsic elements in a hybrid-π equivalent circuit of heterojunction bipolar transistors. This method differs from previous ones by formulating impedance-parameter based expressions that are exclusive of the extrinsic inductances associated with the base, emitter, and collector. It is therefore not susceptible to variation of the extrinsic reactances from DC to high frequencies and can lead to very accurate extraction of the intrinsic elements under different bias conditions. The distributed phenomena in the base region can be also characterized rigorously by exploiting the bias-independent features of the extrinsic elements that are extracted subsequently from knowledge of the intrinsic elements     

Bias sweep rate effects on quasi-static capacitance of MOScapacitors

MOS capacitance measurements are very fundamental characterization methods for MOS and FET structures. This paper discusses the effects of a finite bias sweep rate on quasi-static and high-frequency (HF) capacitance-voltage (C-V) measurements. As typically measured, a finite sweep rate causes the transition region from inversion to depletion of the quasistatic C-V curve to be shifted by several tenths of a volt along the bias voltage axis. The physical origin of this shift as well as a model to account for the effect is discussed. In order to understand quasi-static MOS C-V measurements and to extract fundamental parameters such as substrate doping density and polysilicon depletion effects from C-V measurements, these bias sweep rate effects must be understood and taken into account     

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.     

耦合型漏泄同轴电缆传输和耦合特性研究

针对泄漏同轴电缆作为分布式传感器应用于物联网和智能家居的室内安防入侵检测时，运用全波仿真软件HFSS不能有效仿真长距离的耦合漏缆的问题，提出了一种等效电路模型.利用参数提取软件，先提取单个开槽的缝隙单元的等效电路模型，然后借助于传输线理论，利用四个传输矩阵级联得到整段漏泄同轴电缆的传输矩阵.并考虑两根漏缆缝隙间相互耦合，提出了表征耦合特性的等效电路模型.将等效电路模型利用商用软件高级设计系统（advanced design system，ADS）进行电路搭建与仿真.仿真结果表明，本文提出的两根漏缆的等效电路模型与全波仿真结果非常符合，可以快速地仿真长距离的耦合漏缆结构，并大大节约了仿真时间.     

A Comparative Study of Various MOSFET Models at Radio Frequencies

We have compared and systematically evaluated four mainstream MOSFET models (EKV, SPICE Level 3, Bsim3v3 and Philips MOS Model 9) at radio frequencies. Furthermore, we have tested some improvements proposed for the models in the GHz region. In the first phase complete scalable DC models were determined, and the high frequency model parameters were then extracted from properly designed RF test transistors by using S-parameter fitting and capacitance measurements. The inaccuracies in the AC results were found to be mainly a consequence of the problems in the modelling of the DC conductances. The Bsim3v3 and MOS9 models seem to yield the most realistic AC characteristics of the models. The accuracy of the MOS9 model is slightly inferior to that of the Bsim3v3 model, but it may be improved to the same level or even beyond, simply by adding a gate-bulk zero-bias capacitance to the MOSFET equivalent circuit, which has been done in many commercial circuit simulators. The best models give accurate results up to 4 GHz, and after a careful parameter extraction even at 10 GHz. We also have demonstrated the applicability of the improved models in the design of a LNA CMOS circuit.     

Modeling substrate effects in the design of high-speed Si-bipolarICs

In the design of high-speed IC's, the influence of the substrate on circuit performance must be considered carefully. Therefore, in this paper the contribution of the p^- substrate and channel stopper to the equivalent circuits of Si-bipolar transistors and bond pads are theoretically and experimentally investigated up to very high frequencies. Improved equivalent substrate circuits, well suited for standard circuit simulators (e,g., SPICE), are derived and checked by numerical simulation using a new simulator (called SUSI). The validity of both the numerical simulation results and the equivalent circuits are verified by on-wafer measurements up to 20 GHz. Finally, the simulator was successfully applied to investigate noise coupling via the substrate     

Interface edge effect and its contribution to the frequency dispersion of metal-oxide-semiconductor admittance

Room temperature frequency dispersion of the admittance of Metal-Oxide-Semiconductor (MOS) capacitors made on non-degenerate n-type silicon substrate with (111) surface orientation was studied. A simplified lumped equivalent circuit model which takes into account the interface edge effect, i.e. carrier generation-recombination-trapping via interface states near the edge of the surface inversion region, is proposed and found to be in good agreement with experimental data. Our model also suggests another method of calculating the density of interface states. Fundamental properties of interface states are estimated from experimental data. A self-consistency check is made among the values of equivalent circuit elements to substantiate our model.     

Equivalent circuit modeling of static substrate thermal coupling using VCVS representation

A new method is described which allows substrate thermal coupling between active devices to be accurately represented in a circuit simulation environment. The method, based on a substrate thermal equivalent circuit containing resistors and voltage-controlled voltage sources, allows for exact representation of substrate thermal coupling at any number of evaluation points. The topology of the equivalent circuit and derivation of its coefficients is described, and application of the technique to inter- and intradevice thermal effects is illustrated. The method is applied with a simple self-heating compact model representation to a measured GaAs device characteristic exhibiting gain collapse, and is found to accurately predict electrothermal behavior.