New electronic effects in double injection diodes with one deep level

Double injection diodes made of high resistivity semiconductors compensated with deep levels show a negative differential resistance region in the stationary I - V characteristic. At lower temperatures the injection level of free carriers can be altered within the prebreakdown region without changing the space charge situation. Therefore is valid for several orders of magnitude of the current. Furthermore, the switching of the diode from the “off state” (prebreakdown region) to the “on-state” (high injection or semiconductor regime) can be delayed by applying a corresponding voltage V >V_BD, the breakdown voltage. An exponential dependence of the delay time t_D on the applied voltage is found. The lower limit of t_D is determined by the free carrier lifetime, an upper limit does practically not exist if the temperature is low enough.     

Hot-carrier reliability in deep-submicrometer LATID NMOSFETs

The hot-carrier degradation of large angle tilt implanted drain (LATID) NMOSFETs of a 0.35 μm CMOS technology is analysed and compared to the degradation behaviour of standard LDD devices. LATID NMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity. By means of I–V characterisation and charge pumping measurements, the different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I–V susceptibility to a given amount of generated damage.     

Growth behavior of Cu/Al intermetallic compounds and cracks in copper ball bonds during isothermal aging

Copper wires are increasingly used in place of gold wires for making bonded interconnections in microelectronics. There are many potential benefits for use of copper in these applications, including better electrical and mechanical properties, and lower cost. Usually, wires are bonded to aluminum contact pads. However, the growth of Cu/Al intermetallic compounds (IMC) at the wire/pad interfaces is poorly understood, and if excessive would increase the contact resistance and degrade the bond reliability.To study the Cu/Al IMC growth in Cu ball bonds, high temperature aging at 250 °C for up to 196 h has been used to accelerate the aging process of the bonds. The Cu/Al IMCs growth behavior was then recorded and the IMC formation rate of 6.2 ± 1.7 × 10⁻¹⁴ cm²/s was obtained. In addition to the conventional yz-plane cross-section perpendicular to the bonding interface, a xy-plane cross-section parallel through the interfacial layers is reported. Three IMC layers were distinguished at the Cu/Al interfaces by their different colors under optical microscopy on the xy-plane cross-sections of ball bonds. The results of micro-XRD analysis confirmed that Cu₉Al₄, and CuAl₂ were the main IMC products, while a third phase is found which possibly is CuAl. During the aging process, IMC film growth starts from the periphery of the bond and propagates inward towards the centre area. Subsequently, with increased aging time, cavities are observed to develop between the IMC layer and the Cu ball surface, also starting at the bond periphery. The cavitation eventually links up and progresses toward the centre area leading to a nearly complete fracture between the ball and the intermetallic layer, as observed after 81 h.     

Threshold voltage degradation in plasma-damaged CMOS transistors — Role of electron and hole traps related to charging damage

The paper presents results of study of threshold voltage (V_T) degradation in CMOS transistors damaged by high-field charging. Fowler-Nordheim stress induced V_T degradation in devices with latent charging damage due to plasma processing was found to be strongly dependent on device type and diagnostic stress conditions. “Direct” and “reverse” antenna effect for NMOS, and anomalous behavior of PMOS devices are explained with polarity dependent trapping and the model includes generation of hole traps, an effect not considered previously.     

Effect of wire diameter on the thermosonic bond reliability

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.     

Failure mechanisms of Schottky gate contact degradation and deep traps creation in AlGaAs/InGaAs PM-HEMTs submitted to accelerated life tests

In this work we analyze degradation phenomena observed inpseudomorphic AlGaAs/InGaAs HEMTs with Al/Ti gate metallization, which have been submitted to accelerated tests at high drain-source voltage V_Ds and high power dissipation P_D. After these tests, we observe permanent degradation effects, consisting in electron trapping in the gate-drain access region, with consequent decrease in the longitudinal electric field and “breakdown walkout”, and in thermally-activated interdiffusion of the AI/Ti gate with decrease in the gate Schottky barrier height and increase in drain saturation current I_D. Rather than causing a degradation of therf characteristics of the device, these phenomena induce an increase in the associatedrf gain at 12 GHz, the other rf characteristics being almost unchanged. Overall, the most relevant failure mode observed is an increase of low-frequency transconductance.     

New encapsulation development for fine pitch IC devices

The continuous reduction of chip size driven by the market demand has a significant impact on circuit design and assembly process of IC packages. Shrinking chip size and increasing I/O counts require finer bond pad pitch and bond pad size for circuitry layout. As a result, serious wire deflection during transfer molding process could make adjacent wires short, and this issue becomes more critical as a smaller wire diameter has to be applied for the finer pitch wire bonded IC devices.This paper presents a new encapsulation process development for 50 μm fine pitch plastic ball grid array package. Since reduced wire diameter decreases the bending strength of bonded wires significantly, wire deflection during molding process becomes quite serious and critical. Experiments on conventional transfer molding were conducted to evaluate wire span threshold with 23.0 μm diameter gold wire. The results show that the wire span threshold is about 4.1 mm, which is much shorter than the wire span threshold of over 5.0 mm for wire with 25.4 μm diameter. Finite element analysis shows there is a significant difference in the wire deflection between 23.0 μm gold wire and 25.4 μm gold wire diameter under the same action of mold flow. A novel encapsulation method is introduced using non-sweep solution. The wire span could be extended to over 5.0 mm with wire sweep less than 1%. Reliability tests conducted showed that all the units passed 1000 temperature cycles (−55 to 125 °C) with JEDEC moisture sensitivity level 2a (60 °C/60% relative humidity for 120 h) and 3 times reflow (peak temperature at 220–225 °C). It is believed that this solution could efficiently overcome the risk of wire short issues and improve the yield of ultra fine pitch wire bonds in high-volume production.     

Thermally induced parasitic ungated FET in power MESFETs

The onset of a parasitic FET between the gate and the source (drain) has been observed by monitoring the reverse gate diode I−V characteristics of power GaAs MESFETs, subjected to accelerated aging tests. Such anomalous characteristics are attributed to localized microreactions at the gate metal-GaAs interface, which can be preferential sites for the occurrence of burn-out phenomena.     

Evaluation of SiGe:C HBT intrinsic reliability using conventional and step stress methodologies

The reliability of SiGe:C HBT devices fabricated using the Freescale’s 0.35-μm RF-BICMOS process was evaluated using both conventional and step stress methodologies. This device technology was assessed to determine its capability for various power amplifier applications (e.g., WLAN, Bluetooth, and cellular phone), which are more demanding than conventional circuit designs. The step stress method was developed to allow a rapid evaluation of product reliability, as well as, a quick method to monitor product reliability. For all tests the collector current I_C and collector voltage V_C were kept constant throughout the test, and the current gain β (I_C/I_B) was continuously monitored. The nominal bias condition was V_C = 3.5-V and J_C = 50-kA/cm² (or 0.5-mA/μm²). The “failure criterion” for all reliability evaluations was −10% degradation in β from the initial value at the start of each stress test or interval. The median time to failure (MTTF) at a junction temperature (T_JCN) of 150 °C for the conventional stress test was 1.86E6-h, and the thermal activation energy was 1.33-eV. In contrast for the temperature step stress tests the combined results gave an MTTF at T_JCN = 150 °C of 5.2E6-h and a thermal activation energy of 1.44-eV. Considering the differences in the two test methods, these results are quite close to one another. The intrinsic reliability of this device at the nominal bias condition and T_JCN = 150 °C is more than adequate for a 5-year system life.     

Evaluation of wire bonding performance, process conditions, and metallurgical integrity of chip on board wire bonds

Chip on board wire bonding presents challenges to modern wire bonding technology which include smaller, closely spaced wire bond pads; bonding to soft substrates without special processing and pad construction; and diverse first bond and second bond metallurgies. These challenges are addressed by extensive bonding accuracy tests, a design of experiments approach for optimizing wire bond process parameters, reliability testing, and detailed materials characterization of the metallurgical integrity of the wire bonds. The thermo-mechanical integrity of the wire bond interconnects was evaluated by wire pull and hot storage tests. Hot storage testing allowed for detection of samples with an electrolytic gold surface finish that was too thin, and exhibited a contamination-corrosion condition of the nickel under-plating. Other samples with an excessively thick, rough textured nickel under-plating layer exhibited poor wire bond-ability. The methodology of materials analyses of the metallurgy of the wire bond interconnects is described. The paper illustrates a wire bond lift technique that is used to inspect for cratering damage and the “area-uniformity” of gold aluminum intermetallics. An improved understanding of the wire bonding process was achieved by showing the dependence of the visual appearance of the wire bonds on wire bond process parameters.     

New observations on intermetallic compound formation in gold ball bonds: general growth patterns and identification of two forms of Au4Al

Relatively little information is available on the growth patterns and metallurgy of Au–Al intermetallics in fine-pitch (FP) and ultra-fine pitch (UFP) ball bonding. This paper presents a study of the growth pattern and chemistry of intermetallic compounds formed between a 25 μm 4 N gold wire and aluminium pad metallization after isothermal ageing in air at 175 °C. The data show the intermetallics grow vertically and laterally under the ball and totally consume the Al in the bond pad at <20 h. Then, a third layer of intermetallic grows between Au₄Al and Au₅Al₂. Measurements and observations made with EDX and optical microscopy lead to the conclusion that the new compound is a different form of Au₄Al, most probably a low-temperature version of the α-Au₄Al intermetallic structure. Electrical resistance during intermetallic growth was not measured in this study but wire chemistry and bonding conditions are found to affect the thickness of the intermetallic compounds, which suggests that the resistance of ball bonds during moulding and operation can change.     

Mechanical and electrical characterisation of Au wire interconnects in electronic packages under the combined vibration and thermal testing conditions

This paper concerns the reliability of thermosonically bonded 25 μm Au wires in the combined high temperature with vibration conditions, under which the tests have been carried out on wire-bonded 48-pin Dual-in-Line (DIL) High Temperature Co-fired Ceramic (HTCC) electronic packages. Mechanical, optical and electrical analysis has been undertaken in order to identify the failure mechanisms of bonded wires due to the combined testing. The results indicated a decrease in the electrical resistance after a few hours of testing as a result of the annealing process of the Au wire during testing. In general, ball shear and wire pull strength levels remained high after testing, showing no significant deterioration due to the tests under the combined high temperature and vibration conditions. However, a trend of the variation in the strength values is identified with respect to the combined conditions for all wire-bonded packages, which may be summarised as: (i) increase of the testing temperature has led to a decrease of both the shear and pull strength of the wire bonds; (ii) the mechanical behaviour of the wires is affected due to crystallisation that leads to material softening and consequently the deformation of wire.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Solder joint reliability of a polymer reinforced wafer level package

Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I/O per wafer. Ultra CSP^® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less area arrays at 0.5 mm pitch. This relatively small array has been limited by the inherent solder joint reliability of WLPs. A much larger subset of higher I/O IC’s could benefit from WLPs provided that standard reliability requirements are achieved without the use of underfill.A new polymer reinforcement technology, “Polymer Collar WLP™”, has been developed by K&S Flip Chip Division. Polymer Collar WLP utilizes a polymer reinforcement structure surrounding the solder joint and it has demonstrated more than 50% increase in solder joint life in thermal cycling tests. The most attractive feature of the Polymer Collar WLP process is its simplicity. A simple replacement of the standard solder flux with Polymer Collar material during the solder attach process is all that is required. This simplicity makes Polymer Collar the most cost-effective solution for adding a polymer reinforcement structure to the solder joint. Other methods in use today require additional complex and costly manufacturing steps.This Polymer Collar WLP is expected to widen the WLP market to include larger arrays where the Ultra CSP did not have suitable solder joint reliability.     

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO₂ gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, ΔV_TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO₂ interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO₂ interface (P_b centers) and its vicinity (E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I_D − V_G (ΔV_TH) techniques, however, suggests that ΔV_TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO₂/SiO₂ gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO₂ and high-k gate stacks suggesting a common mechanism of the interface degradation.     

Drain current dlts analysis of recoverable and permanent degradation effects in AlGaAs/GaAs AND AlGaAs/InGaAs HEMT'S

We present a detailed study of drain current DLTS spectra performed on asreceived and failed AlGaAs/GaAs and AlGaAs/InGaAs HEMT's of four different suppliers submitted to hot-electron tests. We demonstrate that a remarkable correlation exists between DLTS features and permanent and recoverable degradation effects. In particular, different behaviours have been found: (i) recoverable effects seems to be correlated with modulation of charge trapped on DX and ME6 centers. (ii) permanent degradation consisting in a decrease in Id and V_T is due to negative charge trapping and is associated with a large increase of a peak having Ea=1.22 eV in the DLTS spectra of failed devices; (iii) development of traps in the gate-to-drain access region induces a permanent increase in drain parasitic resistance Rd and decrease in Id, and is correlated with the growth of a “hole-like” peak in DLTS spectra measured after hot-electron tests.     

Development of “kink” in the output I–V characteristics of pseudomorphic hemt's after hot-electron accelerated testing

Large decreases in the drain current in the linear and low V_ds region followed by a “kink” in the output I_d-V_ds characteristics have been found after hot electron stress test in AlGaAs/InGaAs/GaAs power pseudomorphic HEMT's. Decrease in the transconductance measured in linear region, increase in the drain parasitic resistance and trasconductance frequency dispersion have also been observed and attributed to the generation of electron traps in the gate-to-drain access region.     

The peaks in the electric derivative curves and optic derivative curves of GaAs/GaAlAs high-power QW lasers

The technique of electric derivative measurement can be used for the simple screening of quickly degraded semiconductor lasers. The peaks in electric derivative (I dV/dI−I) and optic derivative curves (dP/dI−I) of GaAs/GaAlAs high-power QW lasers have been investigated. The presence of peaks was used to judge the reliability and quality of devices.     

The influence of solder volume and pad area on Sn–3.8Ag–0.7Cu and Ni UBM reaction in reflow soldering and isothermal aging

This paper examines various aspects of SAC (Sn–3.8Ag–0.7Cu wt.%) solder and UBM interactions which may impact interconnection reliability as it scales down. With different solder joint sizes, the dissolution rate of UBM and IMC growth kinetics will be different. Solder bumps on 250, 80 and 40 μm diameter UBM pads were investigated. The effect of solder volume/pad metallization area (V/A) ratio on IMC growth and Ni dissolution was investigated during reflow soldering and solid state isothermal aging. Higher V/A ratio produced thinner and more fragmented IMC morphology in SAC solder/Ni UBM reflow soldering interfacial reaction. Lower V/A ratio produced better defined IMC layer at the Ni UBM interface. When the ratio of V/A is constant, the IMC morphology and growth trend was found to be similar. After 250 h of isothermal aging, the IMC growth rate of the different bump sizes leveled off. No degradation in shear strength was observed in these solder bump after 500 h of isothermal aging.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.