Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.     

Electrical stress effect on RF power characteristics of SiGe hetero-junction bipolar transistors

In this paper, we investigate the electrical stress effects on both the high-frequency and RF power characteristics of Si/SiGe HBTs. Simultaneously applying a high collector current density and a high collector–base voltage upon the Si/SiGe HBTs, their hot carriers will induce device performance degradation. This stress condition is similar to the DC bias conditions of a current source RF power amplifier, and is termed as a “mixed-mode” stress. We find that not only the maximum oscillation frequency but also the output power performance of Si/SiGe HBTs are suffered by this electrical stress. In addition, the degradations of high-frequency and power characteristics are also worse under a constant base-current measurement than those under a constant collector-current measurement. Finally, we developed a commercial large-signal model to examine the degradations of the parasitic resistances and ideality factors of base and collector currents to explain the RF power and linearity degradations.     

Thermal and package performance limitations in LDMOSFET's for RFICapplications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices     

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device.     

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

一种无源高线性混频组件的设计与实现

在射频通信系统中,混频器作为接收机的核心器件,其线性指标将直接影响整个接收系统的性能。文中设计并实现了一种无源高线性混频组件电路,采用“平衡混频器+吸收式滤波器”的方式达到了高线性要求。平衡混频器采用一对双平衡混频器互联,通过相位抵消达到优化线性的目的;吸收式滤波器吸收混频器产生非线性谐波,使其无法在空间中进行反射,两者共同作用优化了组件整体的线性指标。测试显示,在射频频率为30~1 350 MHz,本振频率为3 030~4 350 MHz,中频频率为3 000 MHz的条件下,混频组件的IIP₂可以达到94 dBm,IIP₃可以达到29 dBm。相比于单独混频器,新电路的线性性能得到极大的优化,更适合高性能的接收机使用。     

High-frequency MOS digital capacitor

A MOS digital capacitor capable of operation at VHF and UHF frequencies is described. This new device is made up of a parallel combination of MOS capacitors each of which can be individually switched between two distinct capacitance values; a maximum binary state being the high-frequency MOS inversion capacity and the minimum being that of a deep-depletion MOS device, Switching is accomplished by on chip MOSFET's. Isolation of the RF terminals is accomplished by the high intervening channel impedances of the switching MOS gates. The basic structure and the principles of operation will be discussed, and operational performance figures for RF tuning range, linearity, dynamic range, and figure of merit Q will be presented.     

Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

A Low-Voltage 5-GHz Downconversion Mixer Employing A Second Harmonic Injection Linearization Technique

In this paper, a low-voltage CMOS mixer topology, appropriate for operation in the 5-GHz frequency band, is presented. The mixer combines several design techniques in order to achieve high linearity performance with minimum current consumption in a restricted 1-V supply. The proposed mixer utilizes an integrated transformer to improve the high frequency performance and to achieve large LO to RF isolation. In addition, a novel linearization technique based on second harmonic injection, is introduced to optimize linearity performance. The design is being implemented in a 0.13-mum CMOS technology.     

Nonlinear source resistance in high-voltage microwave AlGaN/GaN HFETs

Wide bandgap semiconductors are used to fabricate field-effect transistors with significantly improved RF output power compared to GaAs- and InP-based devices. Nitride-based heterostructure field-effect transistors can be biased at high drain voltages, up to and exceeding 100 V, which results in high RF output power. However, the operation of these devices at high drain bias introduces physical phenomena within the device that affect both dc and RF performance. In this study, the existence of a nonlinear source resistance due to space-charge limited current conditions is demonstrated and verified. Inclusion of the nonlinear source resistance in a physics-based device simulator produces excellent agreement between simulated and measured data. The nonlinear source resistance degrades RF performance and limits amplifier linearity.     

Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (t_oxh) and channel length (L_g) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in t_oxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.     

Channel hot-electron degradation on 60-nm HfO/sub 2/-gated nMOSFET DC and RF performances

Channel hot-carrier-induced dc and RF performance degradations in 60-nm high-k nMOSFETs are examined experimentally. RF performances such as the cutoff frequency, noise figure, linearity, and flicker noise of high-k MOSFETs show significant vulnerability to the hot-electron effect. Analytical equations for normalized RF degradations relating to the device dc and ac parameters are derived. Good agreement between the analytical predictions and experimental data is obtained. The accuracy of the model equations suggests fast and effective evaluation of noise figure and linearity degradations using simple dc and ac parameters directly.     

Device linearity improvement byAl0.3Ga0.7As/In0.2Ga0.8Asheterostructure doped-channel FETs

The linearities of pseudomorphic heterostructure Al_0.3Ga_0.7As/In_0.2Ga_0.8As doped-channel FETs (DCFETs) and HEMTs were evaluated by DC and RF testings. Due to the absence of parallel conduction in the doped-channel approach, as compared to the modulation-doped structure, a wide and flat device performance together with a high current density was achieved. This improvement of device linearity suggests that doped-channel designs are suitable for high frequency power device application     

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.     

Hot carrier reliability of RF N- LDMOS for S Band radar application

This paper presents an innovative reliability bench specifically dedicated to high RF power device lifetime tests under pulse conditions for radar application. A base-station dedicated LDMOS transistor has been chosen for RF lifetests and a complete device electric characterization has been performed. A whole review of its critical electrical parameters after accelerated ageing tests is proposed and discussed. This study tend to explain the physical degradation mechanisms occurred during RF life-tests by means of 2D ATLAS-SILVACO simulations. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO2 interface. More interface states are created at low temperature due to a located maximum impact ionization rate at the gate edge.     

LDMOS 功率器件在固态雷达发射系统中应用研究与实践

介绍了LDMOS 功率器件的特性,通过与传统Si 功率器件相比较,LDMOS 器件具有低成本、高增益、高线性度、热稳定性好和高可靠性等特点,在固态雷达发射系统中有广阔的应用前景,本文对LDMOS 功率器件在固态雷达发射系统中应用进行理论分析,并利用LDMOS 功率器件设计制作了P 波段300W 功放组件,对LDMOS 功率放大组件进行性能测试,根据试验数据分析应用LDMOS 功率器件对固态雷达发射系统的影响。     

Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET

In this paper, for the first time, we have analyzed DC characteristics and analog/RF performances for nanowire quadruple-gate (QuaG) gate-all-around (GAA) metal oxide semiconductor field effect transistor (MOSFET), using isomorphic polynomial function for potential distribution. The QuaG GAA MOSFET not only suppresses the short channel effects (SCEs) and offer ideal subthreshold slope (SS), but also is a good candidate for analog/RF device due to its high transconductance (g_m) and high cutoff frequency (f_T). Therefore, this work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. For this, the developed model is based on the solution of 3D Laplace and Poisson׳s equations for subthreshold and strong inversion regions respectively. The developed potential model has been used to formulate a new model for total gate, drain and source charge. Further, the expression for different capacitance for investigating RF performance is obtained from the developed model. Finally, the developed device electrostatics for QuaG GAA MOSFET have been used for the analysis of analog/RF performance. Different capacitances and analog/RF figures of merit are extracted from small signal frequency (1 MHz) ac device simulation. Whereas technology computer-aided design (TCAD) simulations have been performed by 3D ATLAS, Silvaco International.