PZT MIM capacitor with oxygen-doped Ru-electrodes for embedded FeRAM devices

An add-on-type, Pb(Zr,Ti)O/sub 3/ (PZT) metal-insulator- (MIM) capacitor on Al multilevel interconnects is developed for embedded FeRAM devices, concluding that the oxygen-doping into the ruthenium (Ru) electrodes is crucial for obtaining large remnant polarization under a limited process temperature below 450/spl deg/C. The oxygen-doped, Ru bottom-electrode with a granular structure reduces the PZT sputtering temperature below 450/spl deg/C to obtain the ferroelectric perovskite-phase. On the other hand, oxygen doping into the Ru top-electrode suppresses the reductive damage at the interface between the top-electrode and the PZT, keeping the leakage current low. The PZT MIM capacitor with these oxygen-doped, Ru electrodes exhibits the remnant polarization of 21 /spl mu/C/cm/sup 2/ on the Al multilevel interconnects with no degradation of the interconnect reliability, thus applicable to the embedded FeRAM in 0.25 /spl mu/m-CMOS logic LSIs.     

0.18-/spl mu/m nondestructive readout FeRAM using charge compensation technique

A nondestructive readout (NDRO) FeRAM using a 0.18-/spl mu/m CMOS technology has been developed. Readout voltages across the ferroelectric lower than the coercive voltage allowed the FeRAM to achieve high read endurance exceeding required performance for system LSIs, 10/sup 16/ read cycles. The NDRO approach uses a newly developed charge compensation technique to correct the process variations in threshold voltage of neighboring readout transistors, leading to a wide NDRO operation margin over a supply voltage range from 1.1 to 1.8 V.     

Highly reliable ferroelectric memories using BLT thin films and robust integration schemes

We report on highly reliable characteristics of 1-Mb ferroelectric memories based on 0.35-/spl mu/m CMOS technology ensuring ten-year retention and imprint at 175/spl deg/C, which have been successfully developed for the first time. This excellent reliability resulted from newly developed [Bi/sub 1-x/La/sub x/]/sub 4/Ti/sub 3/O/sub 12/ (BLT) ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen.     

Low-temperature capacitor-over-interconnect (COI) Modular FeRAM for SOC application

A complete capacitor-over-interconnect (COI) modular ferroelectric random access memory (FeRAM) is demonstrated. A zero switching time transient approach is adopted to extract the HSPICE model files, and a 128-Kb 1T/1C/ 64-Kb 2T/2C dual function test chip is designed. A novel plate line-driven while bit line (BL)-driven operation scheme is used to achieve fast access speed. In order to build the capacitor-over-interconnect (COI) structure, the FeRAM capacitor must be built at <450/spl deg/C. By using a conductive perovskite LaNiO/sub 3/ (LNO) bottom electrode as seed layer, the crystallization temperature of in situ sputter deposited PZT is greatly reduced to 400/spl deg/C/spl sim/450/spl deg/C. This low processing temperature allows the stacking of ferroelectric capacitor on top of CMOS interconnect. The 2Pr value of the low-temperature grown PZT is about 20 /spl mu/C/cm/sup 2/ and provides 130-400 mV of sensing margin even with high BL capacitance of 800 fF.     

Low thermal-budget process of sputtered-PZT capacitor over multilevel metallization

A low thermal-budget process for fabricating a Pb(Zr, Ti)O/sub 3/ (PZT) capacitor is investigated for application as an embedded FeRAM capacitor on multilevel interconnects. We find that oxygen control is the key factor for reducing the thermal budget of ferroelectrics PZT deposition. Gaseous oxygen retards crystal transformation from the nonferroelectric pyrochlore phase to the ferroelectric perovskite phase, and a supply of oxygen gas during the PZT sputtering encourages deposit of the non-ferroelectric pyrochlore phase. Oxygen-free PZT sputtering on oxygen-doped iridium electrodes, referred to as Ir(O), decreases the deposition temperature for the perovskite PZT, and this process can be used to fabricate ferroelectric capacitors with a thermal budget of 475/spl deg/C /spl times/ 180 s. This low thermal budget does not cause severe damage to the underlying interconnects with Al-wiring and W-vias. This low thermal-budget process can be applied to capacitors for FeRAM on conventional CMOS logic circuits having multilevel interconnects.     

Enhancing leakage suppression in carbon-rich silicon junctions

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.     

A 32-Mb chain FeRAM with segment/stitch array architecture

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.     

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories

A reference generation scheme is proposed for a 1T-1C ferroelectric random-access memory (FeRAM) architecture that balances fatigue evenly between memory cells and reference cells. This is achieved by including a reference cell per row (instead of per column) of the memory array. The proposed scheme converts the bitline voltage to current and compares this current against a reference current using a current-steering sense amplifier. This scheme is evaluated over a range of bitline lengths and cell sizes in a 16-Kb test chip implemented in a 0.35-/spl mu/m FeRAM process. The test chip measures an access time of 62 ns at room temperature using a 3-V power supply.     

On the feasibility of CMOS multiband phase shifters for multiple-antenna transmitters

We present the design of an integrated multiband phase shifter in RF CMOS technology for phased array transmitters. The phase shifter has an embedded classical distributed amplifier for loss compensation. The phase shifter achieves a more than 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured more than 360/spl deg/ phase tuning range in both 3.5-GHz and 5.8-GHz bands. The return loss is less than -10dB at all conditions. The feasibility for transmitter applications is verified through measurements. The output power at a 1-dB compression point (P/sub 1 dB/) is as high as 0.4dBmat 2.4GHz. The relative phase deviation around P/sub 1 dB/ is less than 3/spl deg/. The design is implemented in 0.18-/spl mu/mRF CMOS technology, and the chip size is 1200/spl mu/m /spl times/ 2300 /spl mu/m including pads.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

Improvement of voltage linearity in high-/spl kappa/ MIM capacitors using HfO/sub 2/-SiO/sub 2/ stacked dielectric

It is demonstrated that the voltage coefficients of capacitance (VCC) in high-/spl kappa/ metal-insulator-metal (MIM) capacitors can be actively engineered and voltage linearity can be significantly improved maintaining high capacitance density, by using a stacked insulator structure of high-/spl kappa/ and SiO/sub 2/ dielectrics. A MIM capacitor with capacitance density of 6 fF/spl mu/m/sup 2/ and quadratic VCC of only 14 ppm/V/sup 2/ has been demonstrated together with excellent frequency and temperature dependence (temperature coefficients of capacitance of 54 ppm /spl deg/C) as well as low leakage current of less than 10 nA/cm/sup 2/ up to 4 V at 125 /spl deg/C.     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

Evidence and understanding of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors outperforming sandwich counterparts

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.     

Low-loss, high-voltage 6H-SiC epitaxial p-i-n diode

The p-i-n diodes were fabricated using 31 /spl mu/m thick n/sup -/- and p-type 6H-SiC epilayers grown by horizontal cold-wall chemical vapor deposition (CVD) with nitrogen and aluminum doping, respectively. The diode exhibited a very high breakdown voltage of 4.2 kV with a low on-resistance of 4.6 m/spl Omega/cm/sup 2/. This on-resistance is lower (by a factor of five) than that of a Si p-i-n diode with a similar breakdown voltage. The leakage current density was substantially lower even at high temperatures. The fabricated SiC p-i-n diode showed fast switching with a turn-off time of 0.18 /spl mu/s at 300 K. The carrier lifetime was estimated to be 0.64 /spl mu/s at 300 K, and more than 5.20 /spl mu/s at 500 K. Various characteristics of SiC p-i-n diodes which have an advantage of lower power dissipation owing to conductivity modulation were investigated.     

10-Gb/s modulator drivers with local feedback networks

A novel intrinsic collector-base capacitance (C/sub CB/) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-/spl mu/m SiGe BiCMOS process could generate 9 V/sub PP/ differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 V/sub PP/ in 0.18-/spl mu/m CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers.     

Very large temperature-induced absorptive loss in high Te-containing chalcogenide fibers

The change in the absorption loss relative to room temperature of the infrared (IR)-transmitting Ge/sub 15/As/sub 35/Se/sub (50-x)/Te/sub x/ glass fibers in the temperature range of -110/spl deg/C/spl les/T/spl les/110/spl deg/C was investigated. The attenuation increased significantly at T/spl ges/40/spl deg/C. This is mainly attributed to thermally activated free carriers associated with the semimetallic character of the Te atom. For /spl lambda//spl les/4.2 /spl mu/m, the loss due to electronic and free-carrier absorption was strongly affected by temperature. In the wavelength region of 5-11 /spl mu/m, the loss was mainly due to free-carrier absorption. Beyond /spl lambda//spl ges/11 /spl mu/m, multiphonon absorption dominated the loss spectrum at T/spl les/60/spl deg/C while free-carrier absorption contributed mainly to the total loss at T/spl ges/80/spl deg/C.     

CW operation and threshold characteristics of all-monolithic InAlGaAs 1.55-/spl mu/m VCSELs grown by MOCVD

We demonstrate an all-monolithic metal-organic chemical vapor epitaxy (MOCVD)-grown 1.55-/spl mu/m vertical-cavity surface-emitting laser operating continuous wave up to 35/spl deg/C. The structure is based on the InAlGaAs-InP material system grown by a single step of MOCVD. Wet oxidation of a strained In/sub 0.4/Al/sub 0.6/As layer is used for the current confinement. The threshold current, threshold voltage and the external quantum efficiency at room temperature are about 1.6 mA, 2.3 V, and 5.4%, respectively.     

Strain-compensated InGaAsSb multiple quantum-wells with digital AlGaAsSb barriers for midinfrared lasers

Midinfrared InGaAsSb-AlGaAsSb strain-compensated multiple quantum-wells (SCMQW) have been grown by solid-source molecular beam epitaxy. Short-period (AlGaAsSb)/sub y/--(AlGaSb)/sub 1-y/ digital barriers were employed to avoid growth interruptions at the barrier-well interfaces, thereby significantly improving the structural and optical properties of the InGaAsSb SCMQW as evidenced by X-ray diffraction and photoluminescence measurements. Based on these high-quality SCMQW, a room-temperature threshold current density as low as 163 A/cm/sup 2/ was achieved for 1000-/spl mu/m-long broad-area lasers emitting at 2.38 /spl mu/m in pulsed mode. The 880-/spl mu/m-long lasers retained a high characteristic temperature (T/sub 0/) of 165 K up to 80/spl deg/C and could operate at temperatures above 100/spl deg/C. A typical wavelength blueshift of 38 meV was observed in the SCMQW laser samples compared to the SCMQW-only samples.