80C196MC/MD单片机多个中断程序的同步问题

高性能１６位单片机８ＸＣ１９６ＭＣ／ＭＤ具有指令丰富、外设完善、功能强大等特点。其外设间的协同工作，在测控领域应用中是十分必要的。本文介绍了其外设中断服务程序间的同步控制概念和程序设计应注意的问题。     

一种堆栈型Java处理器的流水线设计

针对目前嵌入式系统的特点，设计了一种四段流水线的堆栈型Java微处理器核。使用双口RAM作为Java栈，减小了存储资源的消耗。通过硬件在一个时钟周期内直接执行Java虚拟机(JVM)中大多数简单的算术／逻辑指令；通过微代码模拟在若干时钟周期内完成中等复杂指令处理；提供硬件陷阱机制，以支持JVM中非常复杂和面向对象指令的软件仿真。综合硬件资源和运行效率两方面的需求可灵活选择不同的指令实现方式，为Java处理器在FPGA中的移植实现提供方便。     

基于Virtex-5和FLASH实现FPGA的多重配置

基于软件无线电平台对FPGA程序加载使用需求,设计了一种FPGA程序重加载电路,分析了软件流程。采用EDA{技术,以Virrex一5系列现场可编程门阵列（FPGA）为核心电路,配合外围存储芯片,在ISE软件中运用VHDL硬件描述语言对1FPGA进行编程以实现设计功能,对功能进行了仿真验证。采用上述方式实现了程序重载的灵活控制。     

基于Zynq的图像角点及边缘检测系统的设计与实现

以Zynq芯片为基础,采用软硬件协同设计的方法设计并实现整个系统。Zynq芯片内部采用ARM+FPGA的异构架构,既具备ARM处理器的灵活性,又拥有FPGA并行处理的能力。本系统的设计充分发挥了Zynq芯片的优势,在软硬件划分上, 通过ARM处理器来实现图像的采集;图像角点及边缘检测用FPGA来完成,即通过硬件加速提升系统的整体性能。ARM处理器与FPGA通过AXI4总线进行数据交互,在Zynq上实现集图像采集、图像特征提取、图像显示为一体的片上系统。最终系统测试结果表明,采用硬件加速实现图像特征提取的相关算法比在ARM处理器软件上实现的算法的速度提高了6～8倍。     

基于FPGA的高速A/D转换控制器设计

采用FPGA器件EP1C12Q240C8实现对高速A/D转换芯片ADC08200的实时采样控制,解决了传统方法的速度问题。使用VHDL语言采用自顶向下的设计方法编写出源程序;结合FIFO存储器的设计实现了高速A/D采集转换和转换后的数据存储,并给出了采样存储电路原理图。数据处理可通过与SoPC技术结合实现。     

基于FPGA的步进电机控制芯片设计

研究了一种以FPGA为基础的步进电机控制芯片的设计,本芯片采用Actel公司的ProASIC3系列FPGA:A3P030进行开发,采用Verilog HDL硬件描述语言进行硬件电路设计,使用Actel公司出品的Libero集成开发环境,通过C8051F060单片机,以C语言为开发语言对设计的芯片进行实际测试.     

PPL: A whole-image processing language

This paper presents the design and implementation of the picture processing language (PPL) that extends the syntax and semantics of traditional image processing libraries. PPL provides a rich set of features to support the development of imaging systems. A main aspect is that many of these features treat a whole-image as an individual operand. An efficient memory management scheme is included that allows “in-place operation” with high memory efficiency.The PPL compiler together with an interpreter can work in two modes. The PPL compiler can convert the source code into C files that can be used as macros within a client program. The program can also be executed at run-time by an interpreter. The dual-execution modes make it possible to be used by both imaging researchers and equipment developers.The extended set of PPL instructions can communicate with digital sensors and 3D displays, and store image data into databases across the Internet. The wavelet-based reverse prediction algorithm can speed up the image loading process approximately three times faster than JPEG. The application programming interface (API) of PPL provides all the building blocks for programmers.     

Multimedia rectangularly addressable memory

We propose a scalable data alignment scheme incorporating module assignment functions and a generic addressing function for parallel access of randomly aligned rectangular blocks of data. The addressing function implicitly embeds the module assignment functions and it is separable, which potentially enables short critical paths and saves hardware resources. We also discuss the interface between the proposed memory organization and a linearly addressable memory. An implementation, suitable for MPEG-4 is presented and mapped onto an FPGA technology as a case study. Synthesis results indicate reasonably small hardware costs in the order of up to a few thousand FPGA slices for an exemplary 512/spl times/1024 two-dimensional (2-D) addressable space and a range of access pattern dimensions. Experiments suggest that speedups close to 8/spl times/ can be expected when compared to linear addressing schemes.     

基于FPGA模拟的阻变神经网络加速器评估方法

基于阻变器件的存算一体神经网络加速器需在架构设计初期进行仿真评估,确保神经网络精度符合设计要求,但传统阻变神经网络加速器的软件模拟器运行速度较慢,难以应对大规模网络的架构评估需求。为加快仿真评估速度,设计一种基于现场可编程门阵列（FPGA）模拟的阻变神经网络加速器评估方法,分析现有阻变神经网络加速器的架构通用性,利用FPGA资源的高度并行性和运行时指令驱动的灵活模拟方式,通过硬件资源的分时复用实现多层次存算一体架构和指令集的功能模拟及主流神经网络的快速性能评估。实验结果表明,针对不同规模的忆阻器阵列和深度神经网络,该评估方法相比MNSIM和DNN NeuroSim软件模拟器运行速度分别提升了40.0~252.9倍和194.7~234.2倍。     

基于状态机的SDRAM控制器的设计与实现

现代计算机的基本框架仍是以冯·诺伊曼结构为基础,以中央控制单元和存储指令/数据的存储器之间的通信为支撑的。同步动态随机存储器(即SDRAM)与静态RAM相比具有容量大,成本低的优势;与传统异步DRAM相比其速度更快,所以得到了越来越广泛的应用。因此以简化主机对SDRAM访问为主要任务的SDRAM控制器的设计就变得更加重要。论文提出了一种基于状态机的SDRAM控制器的设计思路与实现,并通过了FPGA验证,完全达到系统的功能和速度要求。     

基于SOPC的指纹识别模块设计

随着EDA技术及微电子技术的飞速发展,现场可编程门阵列（Field Programmable Gate Array,简称FPGA）的性能有了大幅度的提高。以Nios Ⅱ软核处理器为核心的SOPC（Systemon Programmable Chip）系统便是把嵌入式系统应用在FPGA上的典型例子,本文设计的指纹识别模块就是基于FPGA的Nios Ⅱ处理器为核心的SOPC设计。通过IP核技术和灵活的软硬件编程,实现Nios Ⅱ对FPGA外围器件的控制,利用SOPC Builder将Nios Ⅱ处理器、指纹读取接口UART、键盘与LCD显示接口、FLASH接口、SDRAM控制器构建成Nios Ⅱ硬件系统,后者是电源和时钟电路、SDRAM存储器电路、FLASH存储器电路、LCD显示电路、指纹传感器电路、FPGA配置电路这些纯实物硬件设计。     

数字声波信号处理中的编解码器设计

编解码器是一种能够执行编码和解码数字数据流或信号的设备或程序。该文介绍了基于FPGA设计实现的EDIB总线通信中的曼彻斯特码编解码器,采用Verilog硬件描述语（VerilogHDL）进行设计并集成到FPGA中。在利用FPGA对声波信号处理的过程中,采用状态机,以完成复杂的程序设计,还可以提高仪器的稳定性。这是仪器电...     

异步串行通信下位机的FPGA设计与实现

本文介绍了如何使用FPGA来设计异步串行通信中的下位机,重点分析了FPGA中接收模块的设计要点,并且给出了仿真的时序图;同时给出了一种帧通信协议,介绍了微控制器软核PicoBlaze进行协议解释的处理流程.本文设计的异步通信模块在实际系统中运行稳定可靠,证明了设计方案的正确性.     

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization

In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations.     

一种嵌入式显示系统的软件设计及应用

以高性能的8位单片机C8051F120作为核心处理器,接收和处理PC机键盘和触摸屏的操作信息,并将其转化成液晶显示器(TFT)可显示的点阵数据;用SRAM作为显存,FPGA接收单片机传送的显示数据,控制显存的读写操作,并产生液晶显示器的工作时序,最终完成在液晶显示器上显示字符和65 536色彩色图形的嵌入式设计方案。其中重点描述了核心处理单元C8051F120的软件设计。     

An interactive assembly level debugging system

An interactive assembly level debugging system has been developed to facilitate program development on an INTEL 8080A/8085 based microcomputer. It has features such as decoding machine level instructions into the assembly language, relocating programs in memory, changing instructions interactively at assembly level etc. This paper deals with the design of the assembly level debugging system and the various facilities and features it provides. The debugging system requires only 4.5K bytes of RAM besides the memory requirements of the application program that has to be debugged.     

一种基于DSP在线更新配置程序的实现方法

针对系统设计通用化的需求,设计了一种使用FLASH存储器作为数据存储器件,配合微处理器程序,利用复杂可编程逻辑器件（CPLD）更新和配置可编程器件,实现对现场可编程门阵列（FPGA）程序和数字信号处理器（DSP）程序在线更新的方法。本文给出了系统构成和实现途径,并对ALTERA可编程逻辑器件和TMS320C6000系列DSP的加载和系统设计实现进行了较详细的说明。     

直流电子负载的显示界面设计

随着科技的发展,液晶显示已经在仪器仪表领域得到了广泛的应用。本文所介绍的直流电子负载是基于Mi—crochip公司的PIc32MAx675F257L单片机研制的,其界面显示部分采用的是基于KS0108液晶显示驱动器的128x64点阵的LCD模块。作者详细介绍了电子负载的界面设计流程,并提出了一种新的设计界面的思路和方法。     

基于ARM微控制器配置FPGA的实现

介绍了基于ARM内核的ATMEL AT91FR4081微控制器以JTAG的ISP方式配置XILINX XC2S150PQ208 FPGA的实现过程。这是一种灵活和经济的FPGA的配置方法。介绍了ISP和JTAG的原理、系统实现的流程、硬件电路设计、JTAG驱动算法的实现和配置时间的测试结果。     

A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row × 520-column set covering problem 2,200× faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320× faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600× for the 36-residue protein folding problem.