A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

4×10Gb/s OTDM复用与解复用结构优化技术研究

基于40Gb/s OTDM复用结构,利用电吸收调制器(EAM)及时钟提取模块组成的解复用模型,实现了10GHz时钟分量的提取和信号的解复用.针对OTDM复用后信号的非等幅现象以及对应频谱中含有10GHz、20GHz等其他频谱分量的情况,进行了仿真分析及讨论.同时通过实验对不同的时钟提取与解复用结构提取出的时钟信号的质量进行了对比,优化了解复用结构,得到了抖动更小的帧时钟信号.     

脉幅有序变化OTDM信号的支路及群路全光时钟提取

将含暗帧脉冲的 4× 2 .5GHz的光时分复用 (OTDM)信号注入一含半导体光放大器 (SOA)的锁模光纤激光器 ,利用SOA的交叉增益调制效应 ,提取出 2 .5GHz的支路时钟信号和 5GHz,10GHz的群路时钟信号 ;群路时钟的提取机制是有理数谐波锁模机制。光时分复用信号采用暗帧脉冲不但可以用来识别支路信号 ,而且显著提高了支路时钟信号的质量     

Characterization of the jitter in a mode-locked Er-fiber laser and its application in photonic sampling for analog-to-digital conversion at 10 gsample/s

This paper compares two approaches for evaluating the amplitude and timing jitters of an Er-fiber laser mode-locked at 10 GHz. Using a low-noise oscillator as the clock drive for the mode-locking, relative amplitude jitter was measured as low as 0.0384% and timing jitter as low as 0.0153% (/spl Delta/f=100 Hz-40 MHz). Applying the mode-locked pulse train in a photonic sampling experiment at 10 Gsample/s, a spurious free dynamic range (SFDR) of /spl sim/48.5 dB (over the Nyquist bandwidth of 5 GHz) for multiple analog inputs at L band (1-2.6 GHz). These results correspond to an analog-to-digital conversion resolution of /spl sim/8 SFDR bits at 10 Gsample/s. Finally, the use of "instantaneous companding" is demonstrated to correct for third-order distortions generated by a Mach-Zehnder modulator used in the photonic sampling link.     

100/spl deg/C 10 Gbit/s directly modulated InGaAsP DFB lasers with Ru-doped semi-insulating buried heterostructure

A directly modulated 1.3 /spl mu/m InGaAsP DFB laser with a simple buried structure using Ru-doped semi-insulating InP is presented. The high relaxation oscillation frequency of 10 GHz was obtained at 95/spl deg/C. Clear eye openings under 10 Gbit/s direct modulation were achieved from 0 to 100/spl deg/C.     

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

28 GHz optical injection-locked 1.55 /spl mu/m VCSELs

A record resonance frequency of 28 GHz and an intrinsic laser 3 dB bandwidth of 34 GHz is reported for a directly modulated injection-locked 1.55 /spl mu/m VCSEL. The small-signal modulation response is experimentally investigated using polarisation-maintaining components.     

43 Gb/s decision circuits in InP DHBT technology

Packaged master-slave D-flip-flops designed in InP DHBT technology with 150 GHz f/sub t/ and 180 GHz f/sub max/ are presented. Measurement results using a 43.2 Gb/s nonreturn to zero (NRZ), pseudo random binary sequence (PRBS) data (generated from 4 channels of 10.8 Gb/s, 2/sup 31/-1, PRBS data) and a 43.2 GHz clock, show a clock phase margin of 190/spl deg/. 2:1 Static frequency dividers designed using the D-flip-flops have been tested up to 50 GHz and show normal operation. These circuits are key building blocks in numerous front-end circuits used for 40 Gb/s optical communication systems.     

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.     

160-gb/s optical clock recovery using a regeneratively mode-locked laser diode

Line rate optical clock recovery at 160-Gb/s has been demonstrated based on injection-locking and optical time-division multiplexing of a 40-GHz regeneratively mode-locked laser diode (RML-LD). Injection-locking is achieved by directly coupling the 160-Gb/s data streams to a photodetector in the RML-LD feedback loop. The pulsewidth and root-mean-square timing jitter of the recovered clocks are 2.31 ps and 225 fs (10 Hz-40 MHz), respectively.     

320-to-40-gb/s demultiplexing using a single SOA assisted by an optical filter

We demonstrate excellent all-optical demultiplexing of 40-Gb/s base-rate channels out of 160- and 320-Gb/s single polarization optical time-division-multiplexed data streams. The demultiplexer utilizes a semiconductor optical amplifier and an optical filter placed at the amplifier output. The center wavelength of the filter is blue-shifted from the wavelength of the clock signal, so that ultrafast chirp dynamics can be employed for optical switching. Error-free demultiplexing was achieved at very low optical switch powers: 3.5 mW (160-Gb/s data), 6.3 mW (320-Gb/s data), and 0.09 mW (40-GHz clock). The proposed demultiplexer has a simple structure and allows monolithic integration.     

A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology

A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology.     

Fe-doped InP semi-insulating buried heterostructure for high speed and high power operations in directly modulated semiconductor laser

A buried heterostructure based on Fe-doped InP semi-insulating layers is optimised for both high output power and large modulation bandwidth operations up to 70/spl deg/C in a 10 Gbit/s directly modulated 1.3 /spl mu/m InGaAsP/InP distributed feedback laser. The slope efficiency of 0.19 W/A and -3 dB bandwidth of 10 GHz at 1.5 times threshold current is demonstrated experimentally.     

Optical Clock Recovery Using a Polarization-Modulator-Based Frequency-Doubling Optoelectronic Oscillator

We propose and demonstrate a flexible optical clock recovery scheme using a polarization-modulator-based frequency-doubling optoelectronic oscillator (OEO). The proposed system can extract both prescaled clock and line-rate clock from a degraded high-speed digital signal using only low-frequency devices. A simple theory is developed to study the physical basis of the optical clock recovery. The OEO operation from a free-running mode to an injection-locking mode is investigated. The locking range is quantitatively predicted. An experiment is then implemented to verify the proposed scheme. A prescaled clock at 10 GHz and a line-rate clock at 20 GHz are successfully extracted from a degraded 20 Gb/s optical time-division-multiplexed (OTDM) signal. The locking range and the phase noise performance are also experimentally investigated. Clock recovery from data signals that have no explicit subharmonic tone is also achieved. The proposed system can be modified to extract prescaled clock and line-rate clock from 160 Gb/s data signal using all 40-GHz devices.      

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.     

15-GHz modulation performance of integrated DFB laser diode EA modulator with identical multiple-quantum-well double-stack active layer

Monolithically integrated InGaAsP 1.55-/spl mu/m ridge waveguide distributed feedback laser diodes with an electroabsorption modulator using an identical active multiquantum-well (MQW) layer structure with two different QW types exhibit low-threshold currents <18 mA. The 3-dBe cutoff frequency of 200-/spl mu/m-long modulators exceeds 15 GHz. 10-Gb/s transmission experiments with a voltage swing of 1.0 V/sub pp/ demonstrate the potential of this novel integration scheme.     

以光纤锁模激光器为发射源实现4×10Gbit/sOTDM信号330km传输

本文报导一个以稳定的光纤主动锁模激光器为发射源,以光电振荡器为帧时钟提取装置,以EA调制器为解复用器的4×10Gbit/s光时分复用通信实验系统。该系统成功地实现了单波长40Gbit/s数据信号在330km SMF中的色散补偿传输.     

A 0.18-/spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage.     

Integrated stereo /spl Delta//spl Sigma/ class D amplifier

A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.     

160-gb/s OTDM signal source with 3R function utilizing ultrafast mode-locked laser diodes and modified NOLM

High-quality 160-Gb/s optical time-division-multiplexing (OTDM) signal source with 3R functions was demonstrated using ultrafast mode-locked laser diodes (MLLDs) and a nonlinear optical fiber loop mirror (NOLM) modified with inline and external polarizers and an inline optical phase-bias compensator. Pulse quality for each OTDM channel was successfully improved and equalized owing to the clock extraction at the true data bit rate using a 160-GHz MLLD and also to the improvement of the switching performance of the NOLM.