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1.
In this paper, a MMIC frequency doubler based on an InP HEMT and grounded CPW (GCPW) technology is reported. The doubler demonstrated a conversion loss of only 2 dB and output power of 5 dBm at 164 GHz. The 3 dB output power bandwidth is 14 GHz, or 8.5%. This is the best reported result for a MMIC HEMT doubler above 100 GHz  相似文献   

2.
A broadband frequency doubler using left-handed nonlinear transmission lines(LH NLTLs) based on MMIC technology is reported for the first time.The second harmonic generation on LH NLTLs was analyzed theoretically. A four-section LH NLTL which has a layout of 5.4×0.8 mm~2 was fabricated on GaAs semi-insulating substrate. With 20-dBm input power,the doubler obtained 6.33 dBm peak output power at 26.8 GHz with 24-43 GHz—6 dBm bandwidth.The experimental results were quite consistent with the simulated results.The compactness and the broad band characteristics of the circuit make it well suit for GaAs RF/MMIC application.  相似文献   

3.
The design and characterisation of a 60?GHz frequency quadrupler implemented in a conventional 90?nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15?GHz to 30?GHz doubler, two 30?GHz amplifiers, a polyphase filter, a 30 to 60?GHz doubler and two 60?GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3?dBm at 60?GHz with 1.1?dBm input power is achieved. The 3?dB bandwidth lies between 51.5?GHz and 61?GHz, while the total current consumption is 100?mA from a 1.2?V supply voltage for the fully balanced implementation.  相似文献   

4.
一种基于MMIC技术的宽带左手非线性传输线二次倍频器   总被引:1,自引:1,他引:0  
董军荣  黄杰  田超  杨浩  张海英 《半导体学报》2011,32(9):095003-4
本文首次报道了基于MMIC技术的左手非线性传输线宽带二次倍频器。理论上分析了左手非线性传输线的二次谐波产生原理。在GaAs半绝缘衬底上制作了4节左手非线性传输线,面积为5.4mm*0.8mm。当输入信号为20dBm时,该倍频器在26.4GHz处获得最大二次谐波输出功率为6.33dBm,对应的-6dB带宽为24GHz~43GHz。实验结果与仿真结果吻合良好。以低频放大器作为激励,该倍频器可用于低成本,有效的毫米波甚至THz信号源系统。  相似文献   

5.
A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm2. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.  相似文献   

6.
介绍了一种小型毫米波超宽带平面倍频器。其频带带宽达到三个倍频程,最高工作频率超过42GHz,倍频损耗为10dB±2.2dB,信号抑制不小于10dBc,输入功率动态范围为8dBm~20dBm,具有宽频带、高效率和大动态等特点,可以广泛应用在小型化毫米波平面电路中。  相似文献   

7.
A novel fully differential frequency doubler is proposed based on CMOS technology, where a stacked push-push configuration is used to generate differential output. Compared to previously reported doublers, the proposed topology has advantages in power dissipation, fundamental frequency rejection, and simplicity. By utilising the proposed doubler, a low power direct-conversion up-mixer is designed for 900 MHz applications. The fabricated up-mixer shows 5.5 dB of power conversion gain and 7.5 dBm of output IP3, while dissipating total current of 4.5 mA from 1.25 V supply.  相似文献   

8.
介绍了一种基于肖特基阻性Z-极管的140GHzZ-倍频器,该倍频器采用矩形波导内嵌石英基片微带电路,通过四肖特基结正向并联结构提高驱动功率承受能力。倍频设计中应用了自建精确二极管三维电磁模型、宽带电磁耦合结构和宽带阻抗匹配结构,以提高仿真结果和实际器件的吻合度。测试结果表明:在频率为65GHz一75GHz,功率为20dBm的驱动信号激励下,二倍频器输出频率为130GHz~150GHz,输出功率为3.3dBm~8.0dBm,倍频损耗为11.7dB~16.3dB。在23dBm-24dBm的最大驱动功率激励下,倍频器最大输出功率达11.2dBm/136GHz,基本达到了成像雷达的应用性能指标。  相似文献   

9.
A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.  相似文献   

10.
基于标准的平面肖特基二极管单片工艺设计了一款平衡式亚毫米波倍频单片集成电路。依据二极管实际结构进行电磁建模,提取了器件寄生参数,并与实测的器件本征参数相结合获得了二极管非线性模型;依据该模型,采用平衡式拓扑结构以实现良好的基波抑制,设计了三线耦合巴伦电桥,并与肖特基二极管集成在同一芯片上,实现了单片集成,提高了设计准确度。芯片在片测试结果表明,在输入功率17 dBm 下,输入频率75~105 GHz范围内,倍频器芯片峰值输出功率达到2.67 dBm。芯片整体尺寸为0.80 mm×0.50 mm。  相似文献   

11.
田遥岭  何月  黄昆  蒋均  缪丽 《红外与激光工程》2019,48(9):919002-0919002(6)
高频段的太赫兹信号通常是由多个倍频器级联输出的,因此要求倍频链路的前级必须具备高输出功率的能力。为了提升太赫兹倍频器的功率容量和效率,结合高频特性下肖特基二极管有源区电气模型建模方法,采用高热导率的陶瓷基片,利用对称边界条件,在HFSS和ADS中实现对倍频器电路的分析和优化,研制出了高功率110 GHz平衡式倍频器。最终测试结果表明,驱动功率为28 dBm左右时,该倍频器在102~114.2 GHz的工作带宽内的最高输出功率和效率分别为108 mW和17.6%,为链路后续的二倍频和三倍频提供足够的驱动功率。  相似文献   

12.
介绍了一款基于GaAs肖特基二极管单片工艺的220 GHz倍频器的设计过程以及测试结果。为提高输出功率,倍频器采用多阳极结构,8个二极管在波导呈镜像对称排列,形成平衡式倍频器结构。采用差异式结电容设计解决了多阳极结构端口散射参数不一致问题,提高了倍频器的转换效率和工作带宽。对设计的倍频器进行流片、装配和测试,测试结果显示:倍频器在204~234 GHz频率范围内,转化效率大于15%;226 GHz峰值频率下实现最大输出功率为90.5 mW,转换效率为22.6%。设计的220 GHz倍频器输出功率高,转化效率高,工作带宽大。  相似文献   

13.
基于0.7μm InP HBT工艺,设计实现了一种高功率高谐波抑制比的W波段倍频器MMIC。电路二倍频单元采用有源推推结构,通过3个二倍频器单元级联形成八倍频链,并在链路的输出端加入输出缓冲放大器,进一步提高倍频输出功率。常温25℃状态下,当输入信号功率为0 dBm时,倍频器MMIC在78.4~96.0 GHz输出频率范围内,输出功率大于10 dBm,谐波抑制度大于50 dBc。芯片面积仅为2.22 mm2,采用单电源+5 V供电。  相似文献   

14.
研制了一种基于肖特基变容二极管的0.17 THz 二倍频器, 该器件为0.34 THz 无线通信系统收发前端提供了低相噪、低杂散的本振信号.倍频器结构基于波导腔体石英基片微带电路实现, 其核心器件是多结正向并联的肖特基变容二极管.文中采用结参数模型和三维电磁模型相结合的方式对二极管进行建模, 通过两种电路匹配方式实现了0.17 THz 二倍频器的最优化设计, 最终完成器件的加工及测试.测试结果表明, 在输入80~86 GHz, 20 dBm 的驱动信号下, 倍频器的最大输出功率达12.21 mW, 倍频效率11%, 输出频点为163 GHz;当前端输入功率达到饱和状态时, 该频点输出功率可达21.41 mW.  相似文献   

15.
一种超宽带毫米波倍频器设计   总被引:1,自引:0,他引:1  
叙述了一种超宽带毫米波倍频器的设计,该倍频器由有源差分balun级、对管倍频级和分布式功率放大级三个部分组成。在30—50GHz输出频率范围内,倍频器具有5dB的变频增益,输出功率大于13dBm,基波抑制大于15dB。  相似文献   

16.
Millimeter Wave Varistor Mode Schottky Diode Frequency Doubler in CMOS   总被引:1,自引:0,他引:1  
The first mm-wave varistor mode Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler exhibits 14 dB conversion loss, $-11~{rm dBm}$ output power at 132 GHz and 6 GHz 3-dB output bandwidth from 128 to 134 GHz. The input matching is better than $-10~{rm dB}$ and the rejection of fundamental signal at output is greater than 14 dB from 62 to 70 GHz.   相似文献   

17.
This paper presents Schottky barrier diode circuits fully integrated in a 0.13- mum SiGe BiCMOS process technology. A subharmonically pumped upconverter and a frequency doubler are demonstrated that operate beyond 100 GHz without the need of external components. The upconverter has a size of 430 times 780 mum2 including on-chip matching elements and bond pads. It has a conversion gain of - 6 to - 7 dB from 100 to 120 GHz. The upconverter achieves a high single-sideband saturated output power of - 4 dBm from 100 to 120 GHz and a high linearity with a 1-dB compression point of - 6 dBm. The frequency doubler has a size of 360 times 500 mum2 and can deliver up to 2.5 dBm at 110 GHz.  相似文献   

18.
A V-band frequency doubler monolithic microwave integrated circuit with a current re-use buffer amplifier is presented. The circuit is designed and fabricated using 0.13 $mu$m CMOS technology. The buffer amplifier uses a current re-use topology, which adopts series connection of two common source amplifiers for low dc power consumption. The suppression of the fundamental frequency is obtained by shunting the input frequency at the output node of the doubler and the drain nodes of two common-source stages of the buffer amplifier. The fabricated frequency doubler exhibits an output power of ${-}$4.45 dBm and a conversion gain of ${-}$ 0.45 dB at input frequency of 27.1 GHz with an input power of ${-}$4 dBm. The suppression of the fundamental signal is 49.2 dB. The total dc power dissipation is 9 mW while the buffer amplifier consumes 5 mW. The integrated circuit size including pads is 1.24 mm$, times ,$0.75 mm. To our knowledge, this is the highest suppression with low-power dissipation among V-band frequency doublers.   相似文献   

19.
G-band metamorphic HEMT-based frequency multipliers   总被引:3,自引:0,他引:3  
Two monolithic G-band active frequency multipliers have been designed and fabricated using coplanar-waveguide technology. The monolithic microwave integrated circuits are a frequency tripler for an output frequency of 140 GHz and a 110-220-GHz frequency doubler. The tripler demonstrates a maximum conversion gain of -11 dB for an input power of 9 dBm, whereas the doubler achieves a conversion gain of -7 dB for a 2.5-dBm input signal. The circuits have been realized using two InAlAs/InGaAs-based metamorphic high electron-mobility transistor processes with different gate lengths of 100 and 50 nm, respectively.  相似文献   

20.
Details on a broadband MMIC frequency doubler targeting the MVDS market are presented. The design evolution from an individual pHEMT device to the complete practical doubler realisation is discussed. The doubler MMIC, which has been fabricated using the GMMT H40 GaAs process, has been evaluated in a customised package. An output power of +10 dBm at 40 GHz has been achieved with an associated conversion gain of 1.5 dB. The measured and predicted performance responses are compared. This chip is ideally suited to use in a number of emerging mm-wave applications.  相似文献   

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