The ΣΔ-BIST Method Applied to Analog Filters

This paper describes the -BIST method, defined as an analog BIST circuit in the context of mixed signal systems. The test procedure is based on the reuse of existing analog circuits configured as sigma-delta modulators in the analog domain. The test procedure reuses most of existing blocks in a mixed signal system, and thus has small area overhead. Test sensitivity is very high, detecting small component deviations. Moreover, the proposed test technique can be applied to continuous or sampled time circuits, and the test procedure can be developed in the field. The paper explains the method and presents practical results to validate the proposed approach.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Efficient UBIST implementation for microprocessor sequencing parts

In this paper we first present an improved self-checking solution for the sequencing part of the Motorola MC 68000 microprocessor. compared to previous self-checking proposals for this microprocessor, the present scheme decreases the area overhead and simplifies the complexity of both functional circuits and checkers. In addition, the unified BIST method introduced recently, is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for the integrated circuits, e.g. off-line test for fabrication faults and for maintenance, and on-line concurrent error detection in the field.     

A Statistical Sampler for a New On-Line Analog Test Method

This work shows a new strategy to the on-line test of analog circuits. The technique presents a very low analog overhead and it is completely digital. In the System-on-Chip (SoC) environment the on-line test can be developed by using processing power already available in the system. As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Since it has low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors for reconfiguration, and no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some experimental results illustrating the operation of the Statistical Sampler concerning linear analog systems.     

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.     

Low Cost On-Line Testing Strategy for RF Circuits

This work proposes the use of a simple 1-bit digitizer as an analog block observer, in order to enable the implementation of on-line test strategies for RF analog circuits in the System-on-Chip environment. The main advantages of using a simple digitizer for RF circuits are related to the increased observability of the RF signal path and minimum RF signal degradation, as neither reconfiguration of the signal path nor variable load for the analog RF circuit are introduced. As an additional advantage, the same digitizer can be used to implement BIST strategies, if required. The feasibility of using a 1-bit digitizer for the test of analog signals has already been presented in the literature for low frequency linear analog systems. This paper discusses the implementation of an on-line test strategy for analog RF circuits in the SoC environment, and presents new results for on-line RF testing. Moreover, we also provide detailed analysis regarding the overhead of the test strategy implementation. Experimental results illustrate the feasibility of the proposed technique.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A. Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in VLSI Architecture and is also thesis director. His main research interests are integrated circuit architecture, embedded systems, signal processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.     

Testing analog circuits using spectral analysis

In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.     

Built-in-self-test techniques for MEMS

As predicted by technology roadmaps, embedded micro-electro-mechanical-systems (MEMS) is yet another step in the continuous search for higher levels of integration and miniaturization. MEMS are analog components and the test paradigm is similar to the case of analog and mixed-signal circuits. However, given the fact that they work with signals other than electrical, the test of these embedded parts poses new challenges. In this paper, we will review some recent works in this field and we will present a complete approach to MEMS built-in-self-test (BIST) based on pseudorandom testing.     

Sine-Wave Signal Characterization Using Square-Wave and ΣΔ-Modulation: Application to Mixed-Signal BIST

This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.Diego Vázquez was born in El Coronil, Sevilla, Spain, in 1966. He received the Licenciado en Física degree in 1989 and the Doctor en Ciencias Físicas degree in 1995, both from the University of Sevilla, Spain. Since 1990, he has been with the Departamento de Electrónica y Electromagnetismo, University of Sevilla, where he is a Associate Professor, and also with the Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica (IMSE-CNM-CSIC), Sevilla, Spain. He has published about 100 papers in international journals, books and major conferences. In 1992 he won the Best Paper Award of the 10th IEEE VLSI Test Symposium. His research interests are in the fields of design, fault tolerance, test, and design for testability of analog and mixed-signal circuits.Gloria Huertas was born in Sevilla, Spain, in 1974. She received the Licenciado en Física degree in 1997 and the Ph.D. in 2004, both from the University of Sevilla, Spain. Since then, she has been with the Departamento de Electrónica y Electromagnetismo, University of Sevilla, where she is Assistant Professor, and also with the Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica (IMSE-CNM-CSIC), Sevilla, Spain. Her research focuses on designing electronic mixed-signal circuits and systems including techniques for testability.África Luque was born in Zamora (Spain) in 1977. She received the Licenciado en Física degree in 2000 from the University of Sevilla, Sevilla, Spain. She is with the Departamento de Electrónica y Electromagnetismo, University of Sevilla, and also with the Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica (IMSE-CNM-CSIC), Sevilla, Spain, where she is currently pursuing the Ph.D. degree. Her research focuses on the design and test of mixed-signal circuits including Silicon-On-Insulator technologies.Manuel J. Barragan was born in Sevilla, Spain, in 1980. He received the Licenciado en Física degree in 2003 from the University of Sevilla, Sevilla, Spain. He is currently pursuing the Ph.D. degree from the Instituto de Microelectrónica de Sevilla (IMSE, CNM) on the topics of test and design for testability of analog and mixed-signal circuits.Gildas Leger was born in St. Brieuc, Côtes dArmor, France, in 1976. He received the Ingénieur en Physique degree in 1999 from the National Institute of Applied Sciences (INSA) of Rennes, France.He is currently pursuing the Ph.D. degree from the Instituto de Microelectrónica de Sevilla (IMSE, CNM). His research focuses on designing electronic mixed-signal circuits and systems including techniques for testability, specially in the domain of analog to digital conversion.Adoración Rueda joined the Department of Electronics and Electromagnetism at the University of Seville in 1976 as Assistant Professor, and obtained the Ph.D. degree in 1982. From 1984 to 1996 she was Associate Professor in that Department, where now holds the position of Full Professor in Electronics. In 1989 she became researcher at the Department of Analog Design of the National Microelectronics Center (CNM), now Institute of Microelectronics at Seville (IMSE).She has participated in several research projects financed by the Spanish CICYT and by different programs of the European Community. She has published about 135 papers in international journals, books and major conferences. In 1992 she won the Best Paper Award of the 10th IEEE VLSI Test Symposium. Her research interests are currently focused on the topics of Design and Test of Analog and Mixed-signal Circuits, Behavioral Modeling of Mixed-signal Circuits, and development of CAD tools.Jose Luis Huertas received the Licenciado en Física degree nd the Doctor en Ciencias Físicas degrees in 1969 and 1973, respectively, both from the University of Sevilla, Spain.From 1970 to 1971, he was with the Philips International Institute, Eindhoven, The Netherlands, as a postgraduate student. Since 1971, he has been with the Departamento de Electrónica y Electromagnetismo, University of Sevilla, Spain, where he is a Full Professor. He is also the Director of the Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica de Sevilla, Seville, Spain. His current interests include the design and testing of analog/digital integrated circuits, computer-aided IC analysis and design, fuzzy logic, nonlinear microelectronics, and neural networks.     

An Analog Checker with Input-Relative Tolerance for Duplicate Signals

We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. The key feature of the proposed checker is that it establishes a test criterion that is dynamically adapted to the magnitude of its input signals, thus enhancing the accuracy of assessing their relative discrepancy. Consequently, when this checker is utilized in concurrent error detection, it diminishes the probability of both false negatives and false positives. Likewise, when employed for off-line test purposes, the checker supports both high yield and high fault coverage. In contrast, checkers implementing a static test criterion may only be tuned to achieve efficiently one of the aforementioned objectives.     

基于模拟集成电路BIST的ARMA模块设计

针对模拟集成电路在线测试困难的特点,本文基于BIST结构对模拟集成电路的测试提出了一种新的测试方案,这种算法在测试电路中易于实现,并且容易嵌入到待测芯片中,为模拟集成电路可测试性设计提出了一种新的测试结构和测试算法。     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

A System Design Methodology for Analog Feed Forward Artificial Neural Networks

Today Feed Forward Neural Networks (FFNs) use paradigms tied to mathematical frameworks more than to actual electronic devices. This fact makes analog neural integrated circuits heavy to design. Here we propose an alternative model that can use the native computational properties of the basic electronic circuits. A practical framework is described to train analog FFNs in compliance with the model. This is especially useful whenever the weight storage elements cannot be re-programmed on the fly at a high rate. To show how the capability of such framework can be applied to neural systems with non conventional architectures two cases are presented. The first one is a neural signal processor named NESP which has sigmoidal neurons and the other is an innovative architecture named N-LESS.     

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.     

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.     

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.     

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.