基于蚂蚁算法和遗传算法的时序电路测试生成

为提高时序电路的测试生成效率,该文提出一种新的基于蚂蚁算法和遗传算法的时序电路测试矢量生成算法.针对国际标准时序电路的实验结果表明,该交叉算法既充分发挥了两种算法的优点,又克服了各自的缺点,与其它同类测试生成算法相比,获得了较好的故障覆盖率和测试集.说明采用蚂蚁算法和遗传算法的交叉算法是成功的.     

时序电路等价验证的触发器匹配

通常的时序电路等价性验证方法是将触发器按时序展开,从而将时序电路转化为组合电路进行验证。而一般在待验证的两个时序电路中,触发器是一一对应的,找到触发器的对应关系,时序电路的验证就会得到很大的简化。该文通过一种新的基于布尔可满足性(SAT)算法的自动测试模式生成(ATPG)匹配模型建立联接电路,使用时序帧展开传递算法比较触发器的帧时序状态输出,同时在SAT解算中加入信息学习继承等启发式算法,将时序电路的触发器一一匹配。在ISCAS89电路上的实验结果表明,该文算法在对触发器的匹配问题上是非常有效的。     

数字电路测试向量自动生成系统的比较

把遗传算法与蚂蚁算法运用于组合电路向量自动生成系统,并比较两者性能的优劣,根据实验结果进一步提出优化组合方案,将此方案应用于同步时序电路的测试向量自动生成系统中。提出一种优化的数字电路的测试向量自动生成系统。这个系统集合了蚂蚁算法和遗传算法的优点,使系统能在更短时间生成更小的测试集,而又能达到原先的故障覆盖率。     

一种基于状态转换图的时序电路等价验证算法

提出一种基于状态转换图的时序电路等价验证算法。此算法通过验证两时序电路的状态转换图是否同构．得到两电路是否等价的信息。若两状态转换图同构，则两图中的状态可一一匹配为等价状态对，算法将状态转换图存储为待验证等价状态对的形式，若所有待验证等价状态对均为等价，则两时序电路等价，反之，则不等价。此算法对ISCAS89测试电路进行验证，与基于BDD方法的SIS系统和基于时间帧展开算法相比，均有较好的结果。     

逆向逻辑综合与功能测试建模

本文在分析时序电路故障检测试法存在难题的基础上,提出一种功能测试建模的新方法。具体内容包括:时序电路功能测试建模的要求;利用逆向逻辑综合方法完成同步时序电路测试的建模;以及异步时序电路功能测试建模的特点。这对时序电路功能测试序列的自动生成有重要意义,因为有了这样的模型,时序电路的自动测试生成可归结为图论算法问题。     

时序电路可及状态的枚举和自动测试生成

复杂时序电路的测试生成被公认为VL-SI电路测试的难题之一。本文在分析已发表文献对此问题研究情况的基础上,提出一种实用的、可靠的测试生成方法。本方法的特点有二。一是以时序电路可及状态的分析为依据,建立同步、异步时序电路测试的统一数学模型,完全地、准确地反映电路的稳态功能。二是以图论算法为工具,从电路强连通状态转换图中找出最优测试向量序列。此法适用于数字系统层次或功能测试,有效地降低计算复杂性,加快测试生成速度,可望发展成为VLSI电路实用化测试生成方法的一条新途径。     

基于FSM的时序电路测试生成探析

针对时序电路的结构特点,以有限状态机的状态转换和一致性测试分析为依据,通过采用转换故障模型来实现时序电路的功能测试生成.发现使用VHDL语言和EDA工具软件能很快实现由时序电路到有限状态机的转换,同时可得到时序电路的稳定状态及其有效可及状态.结果表明此方法可实现转换故障的测试生成,是一种研究时序电路功能测试生成的有效方法.     

Fuzzy particle swarm algorithm for function optimization

在传统粒子群算法的基础上运用模糊规则表加入了新的扰动因子,提出了一种新的算法--模糊粒子群算法。算法结合了模糊控制器中输入输出的模糊化处理和粒子群寻优的特点,为实际问题提供了新的解决手段。将模糊粒子群算法应用于函数优化的问题上,通过多组实例数据进行测试,验证表明了本算法具有良好的有效性和鲁棒性。     

时序系统的状态组区别序列测试方法

介绍了采用单变迁故障模型的时序系统状态组区别序列测试方法,通过选择状态组区别序列优化测试序列长度。这种测试生成方法比时序电路门级测试生成快得多,而且能达到很高的故障覆盖率。     

一种基于高维粒子群算法的神经网络结构优化研究

为克服传统BP神经网络在运算过程的不足,提出一种基于高维粒子群算法的神经网络优化方法。通过在高维PSO算法中引入随机变化的加速常数来获得最优权值,对BP神经网络进行优化和训练,再将优化好的高维BP神经网络运用到交通事件自动检测中,通过检测训练算法,并对训练后的数据进行分类测试,把分类测试的结果与传统BP神经网络和经典事件检测算法比较。结果显示,经过优化后的高维粒子群BP神经网络的检测率、算法性能均优于BP神经网络算法和经典算法,其中97,50个测试样本中仅有2个测试样本与应该达到的数值不一致,其他样本都满足测试要求,并且平均优化测试时间是传统BP神经网络检测时间的一半,因此,优化后的BP神经网络算法的性能十分优越。     

A switch-level test generation system for synchronous and asynchronous circuits

A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit.In synchronous circuits, the time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit and synchronous processing between clock phases to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is adaptable to mixed-level test generation.     

基于线性递减系数粒子群优化算法的组卷实现

为了避免目前常用的组卷算法组卷时间长、程序结构复杂、收敛速度慢等缺陷,提出基于线性递减系数粒子群优化算法的组卷策略。通过调整惯性系数,使得步长较小,惯性权系数的变化幅度小,这种减小趋势较为缓慢的方法能够避免陷入局部最优。并对数学模型以及线性递减惯性权系数进行了理论设计,同时通过编程实现了该算法。测试结果表明加入线性递减系数后运算迭代次数明显减少,证明加入线性递减系数后的组卷策略收敛性好,能够高效准确地按照一定的预期条件进行组卷,符合预期要求。     

基于三值多样性粒子群算法的MPRM电路综合优化

通过对离散三值粒子群算法的研究,提出一种三值多样性粒子群算法以求解MPRM（Mixed-Polarity Reed-Muller,MPRM）电路综合优化问题.首先根据混合极性XNOR/OR展开式的特点和几率换算法则,推导出三值粒子群算法的运动方程,在此基础上,采用广泛学习策略和三值变异操作进行算法改进;然后建立三值多样性粒子群算法的粒子与MPRM电路极性的参数映射关系,结合估计模型和XNOR/OR电路混合极性转换方法,将所提算法应用于MPRM电路的最佳功耗和面积极性搜索;最后对10个PLA格式MCNC Benchmark电路进行测试.结果表明：与已发表的方法相比,该文的优化算法表现出了总体显著性的性能优势.     

基于多目标粒子群算法的异构网接入控制

各种异构接入网络的无缝融合是下一代网络的显著体征之一。研究异构网络的呼入接纳控制,考虑延时、价格和阻塞率因素,致力于同时提高运营商收益和用户满意度,将无线异构网络的呼入接纳控制转换为组合优化问题,利用多目标粒子群优化算法收敛速度快,可同时在多目标上进行优化的特点,提出了一种基于多目标粒子群优化算法的异构无线网络呼入接纳控制算法。通过仿真,证明可以在运营商的收益和用户群的满意度中找到好的平衡。     

基于粒子群优化的反潜搜索研究

在分析目前反潜搜索现状的前提下,提出了使用粒子群优化算法进行反潜搜索,并针对基本粒子群优化算法存在早熟和后期收敛速度慢的局限性,对个体极值实行高斯变异,并使惯性因子随进化代数自适应调节,提高了全局搜索能力和后期收敛速度,改进了粒子群优化算法的潜艇搜索策略.经过实验验证,本算法可以有效地提高反潜搜索效率.     

A novel automatic test pattern generator for asynchronous sequential digital circuits

A novel automatic test pattern generator (ATPG) for stuck-at faults of asynchronous sequential digital circuits is presented. The developed ATPG does not require support by any design-for-testability method nor external software tool. The shortest test sequence generation is guaranteed by breadth-first search. The contribution is unique hazard identification before the test generation process, state justification on the gate level, sequential fault propagation based on breadth-first search and stepwise composition of state graphs for sequential test generation. A new six-valued logic together with a new algorithm was developed for hazardous transition identification. The internal combinational ATPG allows to generate test patterns one by one and only if it is required by sequential test generation. The developed and implemented ATPG was tested with speed-independent and quasi-delay-insensitive benchmark circuits.     

混合均值中心反向学习粒子群优化算法

为平衡粒子群算法勘探与开发能力,本文提出混合均值中心反向学习粒子群优化算法.算法将所有粒子和部分优质粒子分别构造的均值中心进行贪心选择,得出的混合均值中心将对粒子所在区域进行精细搜索.同时对混合均值中心进行反向学习,使粒子能探索更多新区域.将本文算法与最新改进的粒子群算法、人工蜂群算法和差分算法在多种测试函数集上进行比较,实验结果验证了混合均值中心反向学习策略的有效性,算法的综合优化性能更强.     

Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced     

TAO: regular expression-based register-transfer level testabilityanalysis and optimization

In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable